TIGER: An efficient timing-driven global router for gate array and standard cell layout design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 11, 1997, Pages 1323-1331

  Hong, Xianlong ^a,b   Xue, Tianxiong ^a,b   Huang, Jin ^a,b   Cheng, Chung Kuan ^a,b   Kuh, E S ^a,b  

^a TSINGHUA UNIVERSITY   (China)

^b SYNOPSYS INC   (United States)

Author keywords

Global router; Layout design; Timing driven, steiner tree

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC CONNECTORS; GATES (TRANSISTOR); TREES (MATHEMATICS);

GLOBAL ROUTER; STEINER TREE;

VLSI CIRCUITS;

EID: 0031271095     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.663822     Document Type: Article

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