Algorithms for non-hanan-based optimization for VLSI interconnect under a higher-order AWE model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 4, 2000, Pages 446-458

  Hu, Jiang ^a   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

Author keywords

Buffer insertion, deep submicron, interconnect, performance optimization, physical design, routing, transistor sizing, vlsi

Indexed keywords

EID: 0001150939     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.838994     Document Type: Article

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