An Efficient Architecture for High Speed Turbo Decoders

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 4, Issue , 2003, Pages 521-524

  Abbasfar, Aliazam ^a   Yao, Kung ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; PARALLEL PROCESSING SYSTEMS; POLYNOMIALS; TURBO CODES;

TURBO DECODERS;

DECODING;

EID: 0141744886     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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2. Frey, B.J.; Kschischang, F.R.; Gulak, P.G. "Concurrent turbo-decoding," Proc. of IEEE International Symp. on Info. Theory, p. 431. July 97.
3. J. Hsu and C.H. Wang, "A parallel decoding scheme for turbo codes," Proc. ISCAS'98, vol.4, June 1998, pp. 445-448.
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9. F. Daneshgaran and K. Yao, "The iterative collapse algorithm: A novel approach to the design of long constraint length Viterbi decoders - Part I," IEEE Trans. on Commun., pp. 1409-1418, Feb. 1995.