Logic design considerations for 0.5-volt CMOS

Proceedings - 2001 Conference on Advanced Research in VLSI, ARVLSI 2001

Volumn , Issue , 2001, Pages 75-85

  Hass, K J ^a   Venbrux, J ^a   Bhatia, P ^a  

^a UNIVERSITY OF NEW MEXICO   (United States)

Author keywords

Circuit testing; CMOS integrated circuits; CMOS logic circuits; CMOS memory circuits; Logic circuits; Logic design; Logic testing; Low voltage; Subthreshold current; Threshold voltage

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; LOGIC DESIGN; THRESHOLD VOLTAGE; VLSI CIRCUITS;

CIRCUIT TESTING; CMOS LOGIC CIRCUITS; CMOS MEMORY CIRCUITS; LOGIC TESTING; LOW VOLTAGES; SUB-THRESHOLD CURRENT;

LOGIC CIRCUITS;

EID: 84951837364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.2001.915552     Document Type: Conference Paper

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