Design, verification, and test of a true single-phase 8-bit adiabatic multiplier

Proceedings - 2001 Conference on Advanced Research in VLSI, ARVLSI 2001

Volumn , Issue , 2001, Pages 42-58

  Kim, Suhwan ^a   Ziesler, C I ^a   Papaefthymiou, M C ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Built in self test; Capacitance; Circuit simulation; Clocks; Design optimization; Energy efficiency; Frequency; Logic design; Logic testing; Power generation

Indexed keywords

CAPACITANCE; CIRCUIT SIMULATION; CLOCKS; CMOS INTEGRATED CIRCUITS; DESIGN; ENERGY EFFICIENCY; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; POWER GENERATION;

DESIGN OPTIMIZATION; EXPERIMENTAL EVALUATION; FREQUENCY; HSPICE SIMULATIONS; LOGIC TESTING; OPERATING FREQUENCY; POWER CLOCK GENERATOR; STANDARD CMOS PROCESS;

BUILT-IN SELF TEST;

EID: 84951755599     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.2001.915549     Document Type: Conference Paper

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