Low-power 16 × 16-b parallel multiplier utilizing pass-transistor logic

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 10, 1999, Pages 1395-1399

  Law, C F ^a   Rofail, S S ^a   Yeo, K S ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; VLSI CIRCUITS;

PARALLEL MULTIPLIERS; PARTIAL PRODUCT ADDER; PARTIAL PRODUCT GENERATOR; PASS TRANSISTOR LOGIC;

MULTIPLYING CIRCUITS;

EID: 0033313815     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.792613     Document Type: Article

References (12)

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