Locally-clocked dynamic logic

Midwest Symposium on Circuits and Systems

Volumn , Issue , 1998, Pages 18-21

  Hoyer, Gregg ^a   Yee, Gin ^a   Sechen, Carl ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; FREQUENCY MULTIPLYING CIRCUITS; PIPELINES;

CIRCUIT SOLUTION; CLOCKING STRATEGIES; DYNAMIC LOGIC; EVENT-DRIVEN; GATE DESIGN; HIGH THROUGHPUT; MULTIPLIER DESIGN; PIPELINE TECHNIQUES;

COMPUTER CIRCUITS;

EID: 0003098476     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.1998.759425     Document Type: Conference Paper

References (6)

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3. Gin Yee and Carl Sechen, "Clock-delayed domino for adder and combinational logic design, " Proc Int. Conf on Computer Design, Austin TX, pp. 332-337, 1996.
4. J. Yuan and C. Svensson, "High-speed CMOS circuit technique, " IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
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6. D. Ghosh and S. K. Nandy, "Design and realization of high performance wave-pipelined 8 × 8 b multiplier in CMOS technology, " IEEE Trans. on VLSI Systems, vol. 3, no. 1, pp. 36-48, March 1995.