An efficient charge recovery logic circuit

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 514-522

  Moon, Yong ^b,c   Jeong, Deog Kyoon ^a,b,c,d,e,f  

^a IEEE

^b Seoul National University

^c Seoul National University   (South Korea)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e TEXAS INSTRUMENTS   (United States)

^f ACM

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; ELECTRIC WAVEFORMS; LOGIC GATES; TIMING CIRCUITS;

CARRY LOOKAHEAD ADDER; CASCODE VOLTAGE SWITCH LOGIC; EFFICIENT CHARGE RECOVERY LOGIC; INDUCTOR BASED SUPPLY CLOCK GENERATION CIRCUIT;

LOGIC CIRCUITS;

EID: 0030125320     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499727     Document Type: Article

References (6)

1. J. S. Denker, "A review of adiabatic computing," in IEEE Symp. on Low Power Electronics, 1994, pp. 94-97.
2. A. G. Dickinson and J. S. Denker, "Adiabatic Dynamic Logic," IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, Mar. 1995.
3. R. T. Hinman and M. F. Schlecht, "Power dissipation measurements on recovered energy logic," in IEEE Symp. on VLSI Circuits Dig. of Tech. Papers, June 1994, pp. 19-20.
4. A. Kramer, J. S. Denker, S. C. Avery, A. G. Dickinson, and T. R. Wik, "Adiabatic computing with the 2N-2N2D logic family," in IEEE Symp. on VLSI Circuits Dig. of Tech. Papers, June 1994, pp. 25-26.
5. L. G. Heller and W. R. Griffin, "Cascode voltage switch logic: A differential CMOS logic family," in ISSCC Dig. Tech. Papers, 1984, pp. 16-17.
6. K. M. Chu and D. I. Pulfrey, "Design procedures for differential cascode voltage switching circuits," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1082-1087, Dec. 1986.