New line in IC design

IEEE Spectrum

Volumn 34, Issue 3, 1997, Pages 52-58

  Lee, Tsu Chang ^a   Cong, Jason ^a  

^a Silicon Valley University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION;

SUBMICRON DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0031100682     PISSN: 00189235     EISSN: None     Source Type: Journal    
DOI: 10.1109/6.576009     Document Type: Article

References (7)

1. K. C. Saraswat F. Mohammadi Effect of Scaling of interconnections on the Time Delay of VLSI Circuits IEEE Transactions on Electron Devices ED-29 4 645 650 April 1982
2. S.-Y. Oh K.-J. Chang 2001 Needs for Multi-Level Interconnect Technology IEEE Circuits & Devices 11 1 16 21 January 1995
3. H.B. Bakoglu interconnections and packaging for VLSI 1990 Addison-Wesley New York
4. J. Cong C.-K. Koh Simultaneous Driver and Wire sizing for Performance and Power optimization IEEE Transactions on VLSI 408 425 December 1994
5. T.-C. Lee Structure Level Adaptations for Artificial Neural Networks 1991 Kluwer Academic Boston
6. B. Preas M. Lorenzetti Physical Design Automation of VLSI Systems 1988 Benjamin/Cummings Calif., Menlo Park
7. Silicon Valley Research Inc. routers http://www.svri.com