Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1998, Pages 369-373

  Ismail, Yehea I ^a   Friedman, Eby G ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; DELAY CIRCUITS; ELECTRIC IMPEDANCE; ELECTRIC LOADS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; PROBLEM SOLVING; SEMICONDUCTOR DEVICE MODELS; VLSI CIRCUITS;

OPTIMUM REPEATER INSERTION; SOFTWARE PACKAGE SPICE;

CMOS INTEGRATED CIRCUITS;

EID: 0031625020     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)