KITE: A behavioural approach to fault-tolerance in FPGA-based systems

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1996, Pages 327-334

  Mojoli, G A ^a   Salvi, D ^a   Sami, M G ^a   Sechi, G R ^a   Stefanelli, R ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; ELECTRIC FAULT CURRENTS; FAULT TOLERANT COMPUTER SYSTEMS; PROBABILITY; REDUNDANCY;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MULTIPLE MODULAR REDUNDANCY TECHNIQUES;

LOGIC GATES;

EID: 0030378849     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)