Hardware assisted two dimensional ultra fast online placement

International Journal of Embedded Systems

Volumn 1, Issue 3-4, 2005, Pages 291-299

  Handa, Manish ^a   Vemuri, Ranga ^a  

^a University of Cincinnati   (United States)

Author keywords

dynamic reconfiguration; online placement; reconfigurable computing

Indexed keywords

EID: 84949686100     PISSN: 17411068     EISSN: 17411076     Source Type: Journal    
DOI: 10.1504/ijes.2005.009957     Document Type: Article

References (18)

1. Bazargan, K., Kastner, R. and Sarrafzadeh, M. (2000) ‘Fast template placement for reconfigurable computing systems’, IEEE Design and Test -Special Issue on Reconfigurable Computing, Vol. 17, No. 1, January–March, pp.68–83.
2. Brebner, G. (1996) ‘A virtual hardware operating system for the Xilinx XC6200’, Proceedings of the 6th International Workshop on Field Programmable Logic and Applications, pp.327–336.
3. Brebner, G. and Diessel, O. (2001) ‘Chip-based reconfigurable task management’, in FPL ’01: Proceedings of the 11th International Conference on Field-Programmable Logic and Applications, Springer-Verlag, London, UK, pp.182–191.
4. Callahan, T.J., Chong, P., DeHon, A. and Wawrzynek, J. (1998) ‘Fast module mapping and placement for datapaths in FPGAs’, in FPGA ’98: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, AGM Press, New York, NY, USA, pp.123–132.
5. Crago, S.P., Schott, B. and Parker, R. (1998) ‘SLAAC: a distributed architecture for adaptive computing’, FPGA for Custom Computin Machines, Proceedings, IEEE Symposium on, April, pp.286–287.
6. Handa, M. and Vemuri, R. (2004a) ‘An efficient algorithm for finding empty space for online FPGA placement’, Proceeding of the 41st Design Automation Conference, AGM Press, New York, NY, USA, pp.960–965.
7. Handa, M. and Vemuri, R. (2004b) ‘An integrated online scheduling and placement methodology’, Proceeding of the Field Programmable Logic and its Applications, August, Springer-Verlag, London, UK, Vol. 3203, pp.444–453.
8. Mulpuri, C. and Hauck, S. (2001) ‘Runtime and quality tradeoffs in FPGA placement and routing’, Proceedings of the 2001 ACM/SIGDA Ninth International Symposium on Field Programmable Gate Arrays, pp.29–36.
9. Singh, H., Lee, M-H., Lu, G., Kurdahi, N., Bagherzadeh, F.J. and Filho, E.C. (2000) ‘MorphoSys:an integrated reconfigurable system for data-parallel and computationintensive applications’, Computers, IEEE Transactions on, Vol. 49, No. 5, pp.465–481.
10. Walder, H., Steiger, C. and Platzner, M. (2003) ‘Fast online task placement on FPGAs: free space partitioning and 2D-hashing’, International Parallel and Distributed Processing Symposium (IPDPS’03), April, p.178.
11. Wigley, G. and Kearney, D. (2001) ‘The first real operating system for recon-figurable computers’, Proceedings of the 6th Australasian Computer Systems Architecture Conference, 2001. ACSAC 2001, pp.130–137.
12. Wrighton, M. and DeHon, A. (2003) ‘Hardware-assisted simulated annealing with application for fast FPGA placement’, Proceedings of the International Symposium on Field-Programmable Gate Arrays, AGM Press, New York, NY, USA
13. Xilinx Inc. (1997) ‘XC6200 field programmeble gate arrays’, April.
14. Xilinx Inc. (2001) JBits Reference Manual Release 2.8, http://www.xilinx.com/products/jbits.
15. Xilinx Inc. (2003) ‘Two flows for partial reconfiguration: module based or small bit manipulations’, Xilinx Application Note No. XAPP290.
16. Youssef, H. and Sait, S.M. (1999) VLSI Physical Design Automation and Practice, World Scientific Publishing Company.
17. Atmel Inc., At40kFPGA Architecture Guide, http://www.atmel.com.
18. Atmel Inc., Implementing Cache Logic with FPGAs: Application Note, http://www.atmel.com.