VLSI layout and packaging of butterfly networks

Annual ACM Symposium on Parallel Algorithms and Architectures

Volumn , Issue , 2000, Pages 196-205

  Yeh, Chi Hsiang ^a   Parhami, Behrooz ^a   Varvarigos, E A ^a   Lee, H ^a  

^a QUEEN S UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; HIERARCHICAL SYSTEMS; LOGIC DESIGN; MICROPROCESSOR CHIPS; MULTICHIP MODULES; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS; STORAGE ALLOCATION (COMPUTER); VLSI CIRCUITS;

BUTTERFLY NETWORKS; THOMPSON MODELS;

MULTIPROCESSING SYSTEMS;

EID: 0033658337     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/341800.341823     Document Type: Article

References (28)