The application of Transmission Line Pulse testing for the ESD analysis of integrated circuits

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 421-429

  Smedes, T ^a   Velghe, R M D A ^a,b   Ruth, R S ^a   Huitsing, A J ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Application specific integrated circuits; Circuit analysis; Circuit testing; Distributed parameter circuits; Electrostatic discharge; Integrated circuit testing; Protection; Pulse circuits; Transmission lines; Voltage

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC LINES; ELECTRIC POTENTIAL; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; PULSE CIRCUITS;

CIRCUIT DESIGNS; CIRCUIT TESTING; CURRENT PATHS; DISTRIBUTED PARAMETER CIRCUIT; ESD ANALYSIS; PROTECTION; TRANSMISSION LINE PULSE TESTING;

ELECTRIC NETWORK ANALYSIS;

EID: 84948994946     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. T. Maloney and N. Khurana, Transmission Line Pulsing Techniques for Circuit Modelling of ESD Phenomena, Proceedings EOS/ESD Symposium 1985, pp. 49-54
2. D.G. Pierce et. al., Electrical Overstress Testing of a 256k UVEPROM to rectangular and double exponential pulses, Proceedings EOS/ESD Symposium, 1988, pp. 137-146
3. G. Notermans, P. de Jong and F. Kuper, Pitfalls when correlating TLP, HBM and MM testing, Proceedings EOS/ESD Symposium, 1998, pp. 170-176
4. W. Stadler et. al., Does the ESD-failure Current Obtained by Transmission Line Pulsing always Correlate to Human Body Model Tests?, Proceedings EOS/ESD Symposium, 1997, pp. 366-372
5. J. Barth et. al., TLP Calibration, Correlation, Standards and New Techniques, Proceedings EOS/ESD Symposium, 2000, pp. 85-96
6. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, John Wiley &Sons, 1995
7. A. Chatterjee and T. Polgreen, A Low-Voltage Triggering SCR for On-Chip Protection at Output and Input Pads, Electron Device Letters, EDL-12, pp. 21-22, 1991
8. G. Notermans, F. Kuper and J. Luchies, Using an SCR as ESD Protection without Latch-up Danger, Proceedings ESREF, Microelectronics &Reliability, Vol. 37pp. 1457-1460, 1997
9. C. Duvvury et. al., Substrate Pump NMOS for ESD Protection Applications, Proceedings EOS/ESD Symposium, 2000, pp. 7-17
10. T. Polgreen and A. Chatterjee, Improving the ESD Failure Threshold of Silicided NMOS Output Transistors by Ensuring Uniform Current Flow, Proceedings EOS/ESD Symposium, 1989, pp. 167-174
11. TMA, Medici-Two-Dimensional Device Simulation Program
12. G. Notermans, On the Use of N-Well Resistors in ESD Protections, Proceedings ESREF, Microelectronics &Reliability, Vol 38, pp. 1741-1748, 1998
13. M. Chaine, S. Smith, A. Bui, Unique ESD Failure Mechanism During Negative to Vcc HBM Tests, Proceedings EOS/ESD Symposium, 1997, pp. 346-355
14. T. Polgreen, Selecting and Implementing the Appropriate ESD Protection strategy, Tutorial E, EOS/ESD Symposium, 1999