On the use of n-well resistors in ESD protections

Microelectronics Reliability

Volumn 38, Issue 11, 1998, Pages 1741-1748

  Notermans, G ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTRIC SHIELDING; ELECTROSTATICS; FAILURE ANALYSIS;

ELECTROSTATIC DISCHARGE;

RESISTORS;

EID: 0032203248     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(98)00177-2     Document Type: Article

References (9)

1. Polgreen T, Chatterjee A. Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow. IEEE Trans Electron Devices 1992;39:379.
2. Scott DB, Bosshart PW, Gallia JD. 1991. US Patent 5,019,888.
3. Carbajal BG, Cline RA, Andresen BH. A successful HBM ESD protection circuit for micron and sub-micron level CMOS. In: EOS/ESD Symposium Proceedings. Rome, NY: ESD Association, 1992:234.
4. Maloney T, Khurana N. Transmission line pulse techniques for circuit modeling of ESD phenomena. In: EOS/ESD Symposium Proceedings. Rome, NY: ESD Association, 1985:49.
5. Kuper F, Bruines J, Luchies JM. Suppression of soft failures in a sub-micron CMOS process. In: EOS/ESD Symposium Proceedings. Rome, NY: ESD Association, 1993:117.
6. Amerasekera A, Chang M, Seitchik J, Chatterjee A, Marayam K, Chern J. Self-heating effects in basic semiconductor structures. IEEE Trans Electron Devices 1993;40:1836.
7. Krieger G, Niles P. Diffused resistor characteristics at high current density levels - Analysis and applications. IEEE Trans Electron Devices 1989;36:416.
8. Hower P, Reddy V. Avalanche injection and second breakdown in transistors. IEEE Trans Electron Devices 1970;17:320.
9. Rountree RN, Hutchins CL. NMOS Protection circuitry. IEEE Trans Electron Devices 1985;32:910.