Optimizing loop performance for clustered VLIW architectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2002-January, Issue , 2002, Pages 271-280

  Qian, Yi ^a   Carr, S ^a   Sweany, P ^b  

^a Michigan Technological University   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Computer architecture; Costs; Delay effects; Embedded system; Energy consumption; Instruments; Modems; Parallel processing; Registers; VLIW

Indexed keywords

COMPUTER ARCHITECTURE; COSTS; DATA TRANSFER; EMBEDDED SYSTEMS; ENERGY UTILIZATION; INSTRUMENTS; INTEGER PROGRAMMING; MODEMS; OPTIMIZATION; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS;

CLUSTERED VLIW ARCHITECTURES; DELAY EFFECTS; HIGH PERFORMANCE EMBEDDED PROCESSORS; INSTRUCTION LEVEL PARALLELISM; INTERCLUSTER COMMUNICATION; PARALLEL PROCESSING; REGISTERS; VLIW;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84948763293     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2002.1106026     Document Type: Conference Paper

References (24)

1. V. Adve, J.-C. Wang, J. Mellor-Crummey, D. Reed, M. Anderson, and K. Kennedy. An integrated compilation and performance analysis environment for data parallel programs. In Proceedings of Supercomputing '95, San Diego, CA, Dec. 1995.
2. A. Aletá, J. Codina, J. Sánchez, and A. González. Graph-partitioning based instruction scheduling for clustered processors. In Proceedings of the 34th Annual International Symposium on Microarchitecture, pages 150-159, Austin, Texas, Dec. 2001.
3. F. Allen and J. Cocke. A catalogue of optimizing transformations. In R. Rustin, editor, Design and Optimization of Compilers, pages 1-30. Prentice-Hall, 1972.
4. P. Briggs, K. D. Cooper, K. Kennedy, and L. Torczon. Coloring heuristics for register allocation. In Proceedings of the ACM SIGPLAN '89 Conference on Programming Language Design and Implementation, pages 275-284, Portland, OR, July 1989.
5. D. Callahan, J. Cocke, and K. Kennedy. Estimating Interlock and Improving Balance for Pipelined Architectures. Journal of Parallel and Distributed Computing, 5:334-358, 1988.
6. A. Capitanio, N. Dutt, and A. Nicolau. Partitioned register files for vliw's: A preliminary analysis of tradeoffs. In Proceedings of the 25th Annual International Symposium on Microarchitecture (MICRO-25), pages 292-300, Portland, OR, December 1-4 1992.
7. S. Carr, C. Ding, and P. Sweany. Improving software pipelining with unroll-and-jam. In Proceedings of the 29th Annual Hawaii International Conference on System Sciences, Maui, HI, January 1996.
8. S. Carr and K. Kennedy. Improving the ratio of memory operations to floating-point operations in loops. ACM Trans. Prog. Lang. Syst., 16(6):1768-1810, 1994.
9. S. Carr and K. Kennedy. Scalar replacement in the presence of conditional control flow. Software Practice and Experience, 24(1):51-77, Jan. 1994.
10. J. Codina, J. Sanchez, and A. Gonzalez. A unified modulo scheduling and register allocation technique for clustered processors. In Proceedings of the 2001 International Conference on Parallel Architectures and Compiler Techniques, Barcelona, Spain, September 2001.
11. J. Hiser, S. Carr, P. Sweany, and S. Beaty. Register partitioning for software pipelining with partitioned register banks. In Proceedings of the 14th International Parallel and Distributed Processing Symposium, pages 211-218, Cancun, Mexico, May 2000.
12. X. Huang, S. Carr, and P. Sweany. Loop transformations for architectures with partitioned register banks. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, pages 48-55, Snowbird, UT, June 2001.
13. D. Kuras, S. Carr, and P. Sweany. Value cloning for architectures with partitioned register banks. In Proceedings of the 1998 Worshop on Compiler and Architecture Support for Embedded Systems, Washington D.C., December 1998.
14. M. Lam. Software pipelining: An effective scheduling technique for VLIW machines. In Proceedings of the ACM SIGPLAN '88 Conference on Programming Language Design and Implementation, pages 318-328, Atlanta, GA, July 1988.
15. E. Nystrom and A. Eichenberger. Effective cluster assignment for modulo scheduling. In Proceedings of the 31st International Symposium on Microarchitecture (MICRO-31), pages 103-114, Dallas, TX, December 1998.
16. D. Poplawski. The unlimited resource machine (URM). Technical Report 95-01, Michigan Technological University, Jan. 1995.
17. Y. Qian. Loop Transformations for Clustered VLIW Architectures. PhD thesis, Department of Computer Science, Michigan Technological University, Houghton, MI, August 2002.
18. B. R. Rau. Iterative modulo scheduling: An algorithm for software pipelined loops. In Proceedings of the 27th Annual International Symposium on Microarchitecture (MICRO-27), November 29-Dec 2 1994.
19. J. Sànchez and A. Gonzàlez. The effectiveness of loop unrolling for modulo scheduling in clustered VLIW architectures. In Proceedings of the 2000 International Conference on Parallel Processing, Toronto, Canada, August 2000.
20. J. Sànchez and A. Gonzàlez. Instruction scheduling for clustered VLIW architectures. In Proceedings of 13th International Symposium on System Systhesis (ISSS-13), Madrid, Spain, September 2000.
21. P. H. Sweany and S. J. Beaty. Overview of the Rocket retargetable C compiler. Technical Report CS-94-01, Department of Computer Science, Michigan Technological University, Houghton, January 1994.
22. Texas Instruments. TMS320C6000 CPU and Instruction Set Reference Guide, 2000. literature number SPRU189.
23. Texas Instruments. TMS320C6000 Optimizing Compiler User's Guide, 2000. literature number SPRU187.
24. J. Zalamea, J. Llosa, E. Ayguadé, and M. Valero. Modulo scheduling with integrated register spilling for clustered VLIW architectures. In Proceedings of the 34th Annual International Symposium on Microarchitecture, pages 160-169, Austin, Texas, Dec. 2001.