Loop transformations for architectures with partitioned register banks

SIGPLAN Notices (ACM Special Interest Group on Programming Languages)

Volumn 36, Issue 8, 2001, Pages 48-55

  Huang, Xianglong ^a   Carr, Steve ^b   Sweany, Philip ^c  

^a Biologically Inspired Neural and Dynamical Systems Laboratory   (United States)

^b Michigan Technological University   (United States)

^c TEXAS INSTRUMENTS   (United States)

Author keywords

D.3.4 Programming Languages : Processors code generation, optimization

Indexed keywords

EID: 0012987131     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/384196.384206     Document Type: Article

References (27)

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