PowerPCTM array verification methodology using formal techniques

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 857-864

  Ganguly, Neeta ^a   Abadir, Magdy ^a   Pandey, Manish ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; BLOCK CODES; EQUIVALENCE CLASSES; FORMAL LOGIC; INTEGRATED CIRCUIT TESTING; PARALLEL PROCESSING SYSTEMS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); EMBEDDED ARRAYS;

MICROPROCESSOR CHIPS;

EID: 0030398539     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)