From VHDL register transfer level to SystemC transaction level modeling: A comparative case study

Proceedings - 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003

Volumn , Issue , 2003, Pages 355-360

  Calazans, N ^a   Moreno, E ^a   Hessel, F ^a   Rosa, V ^a   Moraes, F ^a   Carara, E ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Clocks; Computer aided software engineering; Design automation; Hardware design languages; Integrated circuit modeling; Integrated circuit synthesis; Integrated circuit technology; Network on a chip; Registers; Sockets

Indexed keywords

ABSTRACTING; AUTOMATION; CLOCKS; COMPLEX NETWORKS; COMPUTATIONAL LINGUISTICS; COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DESIGN; ELECTRIC CONNECTORS; HARDWARE; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; MULTIPROCESSING SYSTEMS; SOFTWARE ENGINEERING; SYNTHESIS (CHEMICAL); SYSTEMS ANALYSIS;

DESIGN AUTOMATIONS; HARDWARE DESIGN LANGUAGE; INTEGRATED CIRCUIT MODELING; INTEGRATED CIRCUIT TECHNOLOGY; NETWORK ON A CHIP; REGISTERS;

MODELING LANGUAGES;

EID: 84945376964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2003.1232853     Document Type: Conference Paper

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