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Volumn 2003-January, Issue , 2003, Pages

Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DISCHARGE; MOS DEVICES; SILICIDES;

EID: 84945208714     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (12)
  • 2
    • 0003093425 scopus 로고
    • ESD failure modes: Characteristics, mechanisms and process influences
    • A. Amerasekera et al., "ESD Failure Modes: Characteristics, Mechanisms and Process Influences", IEEE TED-39, p.2, 1992
    • (1992) IEEE TED-39 , pp. 2
    • Amerasekera, A.1
  • 4
    • 0030421382 scopus 로고    scopus 로고
    • Correlating Drain junction scaling, Salicided Thickness, and Lateral NPN behavior with the ESD/EOS performance of a 0.25um CMOS process
    • A. Amerasekera et al., "Correlating Drain junction scaling, Salicided Thickness, And Lateral NPN behavior with the ESD/EOS performance of a 0.25um CMOS process", IEDM 1996, pp. 893-896
    • (1996) IEDM , pp. 893-896
    • Amerasekera, A.1
  • 11
    • 0037972775 scopus 로고    scopus 로고
    • Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design
    • V. A. Vashchenko et al.,"Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design", proc. IRPS 2003, pp 261-268
    • (2003) Proc. IRPS , pp. 261-268
    • Vashchenko, V.A.1
  • 12
    • 33645137480 scopus 로고    scopus 로고
    • Contributions to standardization of transmission line pulse testing methodology
    • B. Keppens et al., "Contributions to standardization of transmission line pulse testing methodology", proc. EOS/ESD 2001, pp. 461-467
    • (2001) Proc. EOS/ESD , pp. 461-467
    • Keppens, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.