Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1997, Pages 308-315

  Bock, K ^a   Russ, C ^a   Badenes, G ^a   Groeseneken, G ^a   Deferm, L ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR);

CHARGED DEVICE MODEL (CDM); ELECTROSTATIC DISCHARGE (ESD); HUMAN BODY MODEL (HBM); TRANSMISSION LINE PULSE (TLP) TEST;

CMOS INTEGRATED CIRCUITS;

EID: 0031332666     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)