Out-of-order vector architectures

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 1997, Pages 160-170

  Espasa, Roger ^a   Valero, Mateo ^a   Smith, James E ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CODES (SYMBOLS); COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; PROGRAM PROCESSORS; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER);

OUT OF ORDER REGISTER RENAMING; OUT OF ORDER VECTOR ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 0031378359     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)