Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Volumn , Issue , 2003, Pages 36-38

  Tadepalli, R ^a   Thompson, C V ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

Bonding processes; Circuit testing; Copper; Integrated circuit interconnections; Integrated circuit technology; Materials science and technology; Surface cleaning; Temperature; Three dimensional integrated circuits; Wafer bonding

Indexed keywords

CHARACTERIZATION; CHEMICAL BONDS; COPPER; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; MATERIALS TESTING; OPTIMIZATION; SURFACE CLEANING; TEMPERATURE; THREE DIMENSIONAL INTEGRATED CIRCUITS; WAFER BONDING;

BONDING PROCESS; CIRCUIT TESTING; INTEGRATED CIRCUIT INTERCONNECTIONS; INTEGRATED CIRCUIT TECHNOLOGY; MATERIALS SCIENCE AND TECHNOLOGY;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84944030663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2003.1219705     Document Type: Conference Paper

References (12)

1. K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A novel chip design for improving deep- submicrometer interconnect performance and systems-on-chip integration," in Proc. of the IEEE, Vol. 89, No. 5, pp. 602-633, 2001.
2. A. Fan, A. Rahman, and R. Reif, Electrochemical and Solid State Letters. 2:534-536, 1999.
3. S. M . Alam, D. E. Troxel, and C. V. Thompson, "A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits," in International Symposium on Quality Electronic Design, March 2002, pp. 246-251.
4. http://www.sematch.org/public/news/conferences/Reliability4/Documents/24 Interconnect Barth.pdf.
5. K. N. Chen, A. Fan, and R. Reif, J. Electron. Mater. Vol.30, No. 4, pp. 331-335, 2001.
6. P. G. Charalambides, J. Lund, A. G. Evans, and R. M. McMeeking, Journal of Applied Mechanics, Vol. 56, pp. 77-82, 1989.
7. K. L. Chavez, and D. W. Hess, J. Electrochem. Soc., Vol. 148, No. 11, pp. G640-G643, 2001.
8. K. T. Turner, A. A. Ayon, D. Choi, B. Miller, and S. M. Spearing, "Characterization of silicon fusion bonds using a four-point bend specimen," in MRS Proc.: Materials Science of Microelectromechanical Systems(MEMS) Devices III, Vol. 657, 2000.
9. C. H. Tsau, S. M. Spearing, and M. A. Schmidt, J.Microelectromechanical Systems, Vol. 11, No. 6, pp. 641-647, 2002.
10. S. Poulston, P. M. Parlett, P. Stone, and M. Bowker, Surface and Interface Analysis, Vol. 24, No. 12, pp. 811-820, 1996.
11. C. A. Desmond-Colinge, and U. Gosele, "Wafer bonding and thinning g in MRS Bulletin, Vol. 23, No. 12, 1998.
12. M. Y. He and J. W. Hutchinson, Int J. Solids Structures, Vol. 25,No. 9 pp. 1053-1067, 1989.