Optimal space compaction of test responses

IEEE International Test Conference (TC)

Volumn , Issue , 1995, Pages 834-843

  Chakrabarty, Krishnendu ^a   Murray, Brian T ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; ERRORS; FAILURE ANALYSIS; FUNCTIONS; GENETIC ALGORITHMS; LOGIC CIRCUITS; LOGIC GATES;

BUILT IN SELF TEST; OPTIMAL SPACE COMPACTION; SINGLE STUCK LINE; TEST RESPONSE;

INTEGRATED CIRCUIT TESTING;

EID: 0029490504     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)