Modified Sakurai-Newton current model and its applications to CMOS digital circuit design

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2003-January, Issue , 2003, Pages 62-69

  Mansour, Makram M ^a   Mansour, Mohammad M ^a   Mehrotra, Amit ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Circuit simulation; CMOS digital integrated circuits; CMOS process; Computational modeling; Degradation; Delay estimation; Digital circuits; Inverters; Predictive models; Semiconductor device modeling

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; CURRICULA; DEGRADATION; DELAY CIRCUITS; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; DRAIN CURRENT; ELECTRIC INVERTERS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICES; SPICE; TRANSISTORS; VLSI CIRCUITS;

CMOS DIGITAL INTEGRATED CIRCUITS; CMOS PROCESSS; COMPUTATIONAL MODEL; DELAY ESTIMATION; PREDICTIVE MODELS;

SEMICONDUCTOR DEVICE MODELS;

EID: 17444405807     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2003.1183354     Document Type: Conference Paper

References (11)

1. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
2. T. Sakurai and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Transactions on Electron Devices, vol. 38, no. 4, pp. 887-894, Apr. 1991.
3. T. Sakurai and A. R. Newton, "Delay analysis of series-connected MOSFET circuits," IEEE Journal of Solid-State Circuits, vol. 26, no. 2, pp. 122-131, Feb. 1991.
4. H. Shichman and D. A. Hodges, "Modeling and simulation of insulated-gate field-effect transistor switching circuits," IEEE Journal of Solid-State Circuits, vol. 3, no. 2, pp. 584-594, Apr. 1990.
5. Makram M. Mansour and N. Shanbhag, "Simplified current and delay models for deep submicron CMOS digital circuits," in IEEE Interenational Conference on Circuits and Systems, vol. 5, pp.109-112, May 2002.
6. Makram M. Mansour, Mohammad M. Mansour, and A. Mehrotra, "Parameterized macrocells with accurate delay models for core-based designs," in IEEE Interenational Symposium on Quality Electronic Design (to appear), Mar. 2003.
7. T. Sakurai, "CMOS inverter delay and other formulas using alpha-power law MOS model," in IEEE Interenational Conference on Computer-Aided Design, pp.74-77, Nov. 1988.
8. S. Kang and Y. Leblebici, CMOS Digital Integrated Circuit Analysis and Design, 2nd ed. New York: McGraw-Hill, 1999.
9. J. M. Rabaey, Digital Integrated Circuits: A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 1996.
10. T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Transaction on Electronic Devices, vol. 40, no. 1, pp. 118-124, Jan. 1993.
11. Makram M. Mansour, Layout generation for deep submicron CMOS circuits, MS thesis, University of Illinois at Urbana-Champaign, 2002.