Transistor aging and reliability in 14nm tri-gate technology

IEEE International Reliability Physics Symposium Proceedings

Volumn 2015-May, Issue , 2015, Pages 2F21-2F25

  Novak, S ^a   Parker, C ^a   Becher, D ^a   Liu, M ^a   Agostinelli, M ^a   Chahal, M ^a   Packan, P ^a   Nayak, P ^a   Ramey, S ^a   Natarajan, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

14nm; Bias Temperature Instability; Fin FET; High k; Hot Carriers; metal gate; Oxide Breakdown

Indexed keywords

HIGH-K DIELECTRIC; HOT CARRIERS; MULTIPLE-GATE FIELD-EFFECT TRANSISTORS; REFRACTORY METAL COMPOUNDS; RELIABILITY; TRANSISTORS;

14NM; BIAS TEMPERATURE INSTABILITY; HIGH- K; METAL GATE; OXIDE BREAKDOWN;

GATE DIELECTRICS;

EID: 84942239866     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2015.7112692     Document Type: Conference Paper

References (12)

1. S. Natarajan et al, "A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0. 0588m2SRAM cell size", International Electon Device Meeting, 2014
2. S. Ramey, et al, "Intrinsic transistor reliability improvements from 22nm tri-gate technology" 2013 International Reliability Physics Symposium, April 2013
3. C. Hu, "Gate Oxide Scaling Limits and Projection", International Electron Device Meeting, 1996
4. S. Ramey, A. Ahsan, J. Hicks, M. Jamil, S. Novak, C. Prasad, A. Rahman, N. Seifert, "Tri-gate Transistor Reliability", International Reliability Physics Symposium, Monday Tutorial, 2014
5. C. Auth et al, "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors", International Electron Device Meeting, 2012
6. S. Pae et al., "BTI Reliability of 45nm High-K + Metal-Gate Process Technology", International Reliability Physics Symposium, 2008
7. S. Ramey, M. Chahal, J. Hicks, P. Nayak, S. Novak, "Transistor Reliability Variation Correlation to Threshold Voltage", International Reliability Physics Symposium, 2015
8. A. Asenov, "Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0. 1 m MOSFET's: A 3-D 'Atomistic' Simulation Study", IEEE Transactions On electron Devices, Vol. 45 12, Dec. 1998
9. B. Kaczer, T. Grasser, Ph. J roussel, J. Franco, R. Degraeve, L.-A. Ragnarsson, E. Simoen, G. Groeseneke, H. Reisinger, "Origin of NBTI Variability in Deeply Scaled pFETs", International Reliability Physics Symposium, 2010
10. C. Prasad et al., "Bias Temperature Instability Variation on SiON/Poly, HK/MG and Trigate Architectures", International Reliability Physics Symposium, 2014
11. J. Franco, B. Kaczer, M. Toledano-Luque, Ph. J. Roussel, g. Groeseneken, B. Schwarz, M. Bina, M. Waltl, P.-J. Wagner, T. Grasser, "Reduction of the BTI Time-Dependent Variability in Nanoscaled MOSFETs by Body Bias", International Reliability Physics Synmposium, 2013
12. S. Barraud, P. Dollfus, S. Galdin, R. Rengel, M. J. Martin, J. E. Velázquez, "An ionised-impurity scattering model for 3-D Monte Carlo device simulation with discrete impurity distribution", Computational Electronics, 2000