-
1
-
-
84866526723
-
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density mim capacitors
-
June
-
C. Auth, et al, "A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors, " 2012 Symposium On VLSI Technology, June 2012. pp. 131-132.
-
(2012)
2012 Symposium on VLSI Technology
, pp. 131-132
-
-
Auth, C.1
-
2
-
-
84938243329
-
A 14nm logic technology featuring 2nd-generation finfet, air-gapped interconnects, self-aligned double patterning and a 0. 0588um2 SRAM cell size
-
S. Natarajan, et al., "A 14nm Logic Technology Featuring 2nd-Generation FinFET, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0. 0588um2 SRAM cell size, " IEDM 2014. pp. 3. 7. 1-3. 7. 3.
-
(2014)
IEDM
, pp. 371-373
-
-
Natarajan, S.1
-
3
-
-
84880062300
-
Superior PBTI reliability for SOI FinFET technologies and its physical understanding
-
July
-
M. Wang, et al, "Superior PBTI Reliability for SOI FinFET Technologies and Its Physical Understanding, " IEEE EDL, vol. 34, no. 7, July 2013, pp. 837-839.
-
(2013)
IEEE EDL
, vol.34
, Issue.7
, pp. 837-839
-
-
Wang, M.1
-
4
-
-
77957904660
-
Origin of NBTI variability in deeply scaled pFETs
-
B. Kaczer, T. Grasser, Ph. J. Roussel, J. Franco, R. Degraeve, L.-A. Ragnarsson, E. Simoen, G. Groeseneken, H. Reisinger, "Origin of NBTI Variability in Deeply Scaled pFETs, " IRPS 2010, pp. 2A3. 1-2A3. 7.
-
(2010)
IRPS
, pp. 2A31-2A37
-
-
Kaczer, B.1
Grasser, T.2
Roussel, P.J.3
Franco, J.4
Degraeve, R.5
Ragnarsson, L.-A.6
Simoen, E.7
Groeseneken, G.8
Reisinger, H.9
-
5
-
-
84905665875
-
Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures
-
C. Prasad, et al., "Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures, " IRPS 2014, pp. 6A. 5. 1-6A. 5. 7.
-
(2014)
IRPS
, pp. 6A51-6A57
-
-
Prasad, C.1
-
6
-
-
84880982123
-
Reduction of the BTI time-dependent variability in nanoscaled mosfets by body bias
-
J. Franco, et al. "Reduction of the BTI Time-Dependent Variability in Nanoscaled MOSFETs by Body Bias, " IRPS 2013, pp. 2D3. 1-2D3. 6.
-
(2013)
IRPS
, pp. 2D31-2D36
-
-
Franco, J.1
-
7
-
-
84880988341
-
Intrinsic transistor reliability improvements from 22nm tri-gate technology
-
S. Ramey et al, "Intrinsic Transistor Reliability Improvements from 22nm Tri-Gate Technology, " IRPS 2013. p. 4C. 5. 1.-4C. 5. 5.
-
(2013)
IRPS
, pp. 4C51-4C55
-
-
Ramey, S.1
-
9
-
-
84942239866
-
Transistor aging and reliability in 14nm tri-gate technology
-
S. Novak, M. Chahal, P. Nayak, M. Liu, C. Parker, D. Beecher, S. Ramey, "Transistor Aging and Reliability in 14nm Tri-Gate Technology, " IRPS 2015.
-
(2015)
IRPS
-
-
Novak, S.1
Chahal, M.2
Nayak, P.3
Liu, M.4
Parker, C.5
Beecher, D.6
Ramey, S.7
-
10
-
-
84942892765
-
Reliability characterization of 32nm high-k and metal gate logic transistor technology
-
S. Pae, et al, "Reliability Characterization of 32nm High-K and Metal Gate Logic Transistor Technology, " IRPS 2010. pp. 3D2. 1-3D2. 6
-
(2010)
IRPS
, pp. 3D21-3D26
-
-
Pae, S.1
-
11
-
-
84905649489
-
Correlation of bti induced device parameter degradation and variation in scaled metal gate / high-k CMOS technologies
-
A. Kerber and T. Nigam, "Correlation of BTI induced device parameter degradation and variation in scaled Metal Gate / High-k CMOS technologies, " IRPS 2014. pp. 6A. 6. 1-6A. 6. 6.
-
(2014)
IRPS
, pp. 6A61-6A66
-
-
Kerber, A.1
Nigam, T.2
-
12
-
-
33645403754
-
NBTI impact on transistor & circuit: Models, mechanisms, & scaling effects
-
A. Krishnan, et al., "NBTI Impact on Transistor & Circuit: Models, Mechanisms, & Scaling Effects, " IEDM 2003. pp. 14. 5. 1-14. 5. 4
-
(2003)
IEDM
, pp. 1451-1454
-
-
Krishnan, A.1
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