A time digitizer CMOS gate-array with a 250 ps time resolution

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 2, 1996, Pages 212-220

  Arai, Yasuo ^a,b,c,d   Ikeno, Masahiro ^a,b,e  

^a HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION KEK   (Japan)

^b Waseda University ^*

^c TOHOKU UNIVERSITY   (Japan)

^d National Laboratory for High Energy Physics   (Japan)

^e IEEE

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; ELECTRIC FREQUENCY CONTROL; GATES (TRANSISTOR); OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS;

DUAL PORT MEMORIES; SEA OF GATE TECHNOLOGY; TIME DIGITIZER; TIME MEMORY CELL; TIME RESOLUTION;

TIMING CIRCUITS;

EID: 0030082886     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.487998     Document Type: Article

References (11)

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