Multi-Strata Stealth Dicing before Grinding for Singulation-Defects Elimination and Die Strength Enhancement: Experiment and Simulation

IEEE Transactions on Semiconductor Manufacturing

Volumn 28, Issue 3, 2015, Pages 408-423

  Teh, Weng Hong ^a,b   Boning, Duane S ^a   Welsch, Roy E ^b  

^a Department of Electrical Engineering and Computer Science   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

defects; laser.; Semiconductor device manufacture; semiconductor device packaging; semiconductor memory; wafer dicing

Indexed keywords

CHIP SCALE PACKAGES; DEFECTS; DIES; GRINDING (MACHINING); LASERS; PULSED LASERS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; SEMICONDUCTOR LASERS; SEMICONDUCTOR STORAGE; SILICON WAFERS; SURFACE DEFECTS; ULTRAFAST LASERS;

DIE ATTACH FILM; INTEGRATION APPROACH; INTERFERENCE EFFECTS; NANOSECOND PULSED LASER; SEMICONDUCTOR DEVICE PACKAGING; SEMICONDUCTOR MEMORY; SURFACE ABLATION; WAFER DICING;

ELECTRONICS PACKAGING;

EID: 84938807085     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2015.2438875     Document Type: Article

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