P-SOCRATES: A Parallel Software Framework for Time-Critical Many-Core Systems

Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014

Volumn , Issue , 2014, Pages 214-221

  Pinho, Luis Miguel ^a   Quiñones, Eduardo ^b   Bertogna, Marko ^c   Marongiu, Andrea ^d   Carlos, Jorge Pereira ^e   Scordino, Claudio ^f   Ramponi, Michele ^g  

^a INSTITUTO SUPERIOR DE ENGENHARIA DO PORTO   (Portugal)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

^c UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^d ETH ZURICH   (Switzerland)

^e ATOS   (Spain)

^f Evidence Srl   (Italy)

^g Active Technologies Srl   (Italy)

Author keywords

Many core systems; Parallel programming; Predictability; Real Time; Scheduling

Indexed keywords

COMMERCIAL OFF-THE-SHELF; PARALLEL PROGRAMMING; SCHEDULING;

HIGH PERFORMANCE COMPUTING (HPC); MANY CORE; PARALLEL SOFTWARE FRAMEWORK; PERFORMANCE CAPABILITY; PERFORMANCE REQUIREMENTS; PREDICTABILITY; REAL TIME; SCHEDULABILITY ANALYSIS;

REAL TIME SYSTEMS;

EID: 84928788409     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2014.94     Document Type: Conference Paper

References (38)

1. P-SOCRATES (Parallel Software Framework for Time-Critical Many-core Systems) http://p-socrates.eu.
2. OpenMP Architectural Review Board, OpenMP Application Program Interface, Version 4.0, http://www.openmp.org, July 2013.
3. J. Engblom A. Ermedahl. Execution time analysis for embedded real-time systems. Handbook of Real-Time Embedded Systems, January 2007.
4. AbsInt Corp. aiT WCET analyser, http://www.absint.com/ait/.
5. Cédric Augonnet, Samuel Thibault, Raymond Namyst, and Pierre-André Wacrenier. Starpu: A unified platform for task scheduling on heterogeneous multicore architectures. Concurr. Comput. : Pract. Exper., 23(2):187-198, February 2011.
6. S. Baruah, V. Bonifaci, A. Marchetti-Spaccamela, L. Stougie, and A. Wiese. A generalized parallel task model for recurrent realtime processes. In Real-Time Systems Symposium (RTSS), 2012 IEEE 33rd, pages 63-72, 2012.
7. Sanjoy Baruah and Kirk Pruhs. Open problems in real-time scheduling. Journal of Scheduling, 13(6):577-582, 2010.
8. Luca Benini, Eric Flamand, Didier Fuin, and Diego Melpignano. P2012: building an ecosystem for a scalable, modular and highefficiency embedded computing accelerator. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE '12, pages 983-987, San Jose, CA, USA, 2012. EDA Consortium.
9. Robert D. Blumofe and Charles E. Leiserson. Scheduling multithreaded computations by work stealing. J. ACM, 46(5):720-748, September 1999.
10. Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, and Mateo Valero. A dynamic scheduler for balancing hpc applications. In Proceedings of the 2008 ACM/IEEE conference on Supercomputing, SC '08, pages 41:1-41:12, Piscataway, NJ, USA, 2008. IEEE Press.
11. Javier Bueno, Luis Martinell, Alejandro Duran, Montse Farreras, Xavier Martorell, Rosa M. Badia, Eduard Ayguade, and Jes us Labarta. Productive cluster programming with ompss. In Proceedings of the 17th international conference on Parallel processing-Volume Part I, Euro-Par'11, pages 555-566, Berlin, Heidelberg, 2011. Springer-Verlag.
12. Dakshina Dasari, Bjorn Andersson, Vincent Nelis, Stefan M. Petters, Arvind Easwaran, and Jinkyu Lee. Response time analysis of cots-based multicores considering the contention on the shared memory bus. In Proceedings of the 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications, TRUSTCOM '11, pages 1068-1075, Washington, DC, USA, 2011. IEEE Computer Society.
13. Alejandro Duran, Eduard Ayguadé, Rosa M. Badia, Jesus Labarta, Luis Martinell, Xavier Martorell, and Judit Planas. Ompss: A proposal for programming heterogeneous multi-core architectures, 2011-03-01 2011.
14. T. Ungerer et. al. Merasa: Multi-core execution of hard real-time applications supporting analysability. In In the IEEE Micro 2010, Special Issue on European Multicore Processing Projects, Vol. 30, No. 5, Oct. 2010.
15. Mike Houston, Ji-Young Park, Manman Ren, Timothy Knight, Kayvon Fatahalian, Alex Aiken,William Dally, and Pat Hanrahan. A portable runtime interface for multi-level memory hierarchies. In Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, PPoPP '08, pages 143-152, New York, NY, USA, 2008. ACM.
16. Intel Corp. Array Building Blocks, http://software.intel.com/enus/ articles/intel-array-buildingblocks.
17. Intel Corporation. Intel Many Integrated Core (MIC) Architecture-http://www.intel.com/content/www/us/en/architectureand-technology/many-integratedcore/ intel-many-integrated-corearchitecture. html, last access Nov 2013.
18. Intel Corporation. Intel Xeon Phi-http://www.intel.com/content/www/us/en/ processors/xeon/xeonphi-detail.html, last access Nov 2013.
19. R.M. Badia J. Labarta J.M. Perez, P. Bellens. Cellss: Making it easier to program the cell broadband engine processor, 2007.
20. Kalray Corporation. Kalray MPPA 256-http://www.kalray.eu/products/mppa-manycore/, last access Nov 2013.
21. K. Lakshmanan, S. Kato, and R. Rajkumar. Scheduling parallel real-time tasks on multi-core processors. In Real-Time Systems Symposium (RTSS), 2010 IEEE 31st, pages 259-268, 2010.
22. David C. Luckham. The Power of Events: An Introduction to Complex Event Processing in Distributed Enterprise Systems. Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 2001.
23. T. Lundqvist and P. Stenstrom. Timing anomalies in dynamically scheduled microprocessors. In Real-Time Systems Symposium, 1999. Proceedings. The 20th IEEE, pages 12-21, 1999.
24. José Manuel Marinho, Stefan M. Petters, and Marko Bertogna. Extending fixed task-priority schedulability by interference limitation. In Proceedings of the 20th International Conference on Real-Time and Network Systems, RTNS '12, pages 191-200, New York, NY, USA, 2012. ACM.
25. Mont-Blanc FP7 European Project, grant agreement 288777. http://www.montblanc-project.eu/, 2011-2014.
26. L. Nogueira, J.C. Fonseca, C. Maia, and L.M. Pinho. Dynamic global scheduling of parallel real-time tasks. In Computational Science and Engineering (CSE), 2012 IEEE 15th International Conference on, pages 500-507, 2012.
27. NVIDIA Corporation. NVIDIA CUDA Compute Unified Device Architecture, Version 2.0, 2008.
28. Stephen L Olivier, Allan K Porterfield, Kyle B Wheeler, Michael Spiegel, and Jan F Prins. Openmp task scheduling strategies for multicore numa systems. Int. J. High Perform. Comput. Appl., 26(2):110-124, May 2012.
29. OpenCL. The open standard for parallel programming of heterogeneous systems-http://www.khronos.org/opencl/, 2013.
30. parMERASA FP7 European Project-grant agreement 287519. Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability, http://www.parmerasa.eu, 2011-2014.
31. Rapita Systems Corp. RapiTime, http://www.rapitasystems.com.
32. A. Saifullah, K. Agrawal, Chenyang Lu, and C. Gill. Multi-core real-time scheduling for generalized parallel task models. In Real-Time Systems Symposium (RTSS), 2011 IEEE 32nd, pages 217-226, 2011.
33. Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, and Pat Hanrahan. Larrabee: A many-core x86 architecture for visual computing. ACM Trans. Graph., 27(3):18:1-18:15, August 2008.
34. Herb Sutter. Welcome to the jungle, http://herbsutter.com/welcome-to-the-jungle/.
35. R. Tieman. Algo trading: The dog that bit its master. Financial Times, March, 2008.
36. Tilera Corporation. Tile Processor, User Architecture Manual, release 2.4, DOC.NO. UG101, May 2011.
37. Sandra Wienke, Paul Springer, Christian Terboven, and Dieter an Mey. Openacc: first experiences with real-world applications. In Proceedings of the 18th international conference on Parallel Processing, Euro-Par'12, pages 859-870, 2012.
38. Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham Chinya, Ankur Khandelwal Groen, Hong Jiang, and HongWang. Pangaea: A tightly-coupled ia32 heterogeneous chip multiprocessor. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques, PACT '08, pages 52-61, 2008.