1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling Array Processor

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 603-606

  Karakiewicz, Rafal ^a   Genov, Roman ^a   Cauwenberghs, Gert ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b UNIVERSITY OF CALIFORNIA SAN DIEGO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY PROCESSING; INTEGRATED CIRCUITS; STOCHASTIC SYSTEMS;

CHARGE RECYCLING; DC SUPPLIES; LOAD-BALANCED; MIXED SIGNAL; ON-CHIP CAPACITANCE; SINGLE WIRES; STOCHASTIC DATA; UNIT CELLS;

MIXED SIGNAL INTEGRATED CIRCUITS;

EID: 84924737520     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405804     Document Type: Conference Paper

References (10)

1. A. Wang, A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology, " IEEE JSSC, Vol. 40, No. 1, pp. 310-319, Jan. 2005.
2. H. Yamauchi, H. Akamatsu, T. Fujita, "An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's, " IEEE JSSC, Vol. 30, No. 4, pp. 423-431, April 1995.
3. Y. Moon, D. K. Jeong, "An efficient charge recovery logic circuit, " IEEE JSSC, Vol. 31, No. 4, pp. 514-522, April 1996.
4. J. Ammer, M. Bolotski, P. Alvelda, T. F. Jr Knight, "160x120 pixel liquidcrystal-on-silicon microdisplay with an adiabatic DAC, " IEEE ISSCC, pp. 212-213, 1999.
5. W. Athas, N. Tzartzanis, W. Mao, L. Peterson, R. Lal, K. Chong, Joong-Seok Moon; L. Svensson, M. Bolotski, "The design and implementation of a low-power clock-powered microprocessor, " IEEE JSSC, Vol. 35, No. 11, pp. 1561-1570, Nov. 2000.
6. R. Karakiewicz, R. Genov, A. Abbas and G. Cauwenberghs, "175 GMACS/mW Charge-Mode Adiabatic Mixed-Signal Array Processor, " Proc. IEEE 2006 Symp. VLSI Circuits, Honolulu HI, Jun 13-17, 2006.
7. A. Nakada, T. Shibata, M. Konda, T. Morimoto, and T. Ohmi, "A Fully Parallel Vector-Quantization Processor for Real-Time Motion-Picture Compression", IEEE JSSC, Vol. 34, No. 6, pp. 822-830, June 1999.
8. T. Yamasaki, T. Nakayama, and T. Shibata, "A low-power and compact CDMA matched filter based on switched-current technology", IEEE JSSC, Vol. 40, No. 4, pp. 926-932, Apr. 2005.
9. R. Genov, G. Cauwenberghs, G. Mulliken, F. Adil, "A 5. 9mW 6. 5GMACS CID/DRAM Array Processor, " Proc. European Solid-State Circuits Conference (ESSCIRC'2002), Florence Italy, Sept. 24-26, 2002.
10. R. Genov and G. Cauwenberghs, "Stochastic Mixed-Signal VLSI Architecture for High-Dimensional Kernel Machines, " Adv. Neural Information Processing Systems (NIPS'2001), Cambridge: MIT Press, vol. 14, 2002.