High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

Eurasip Journal on Image and Video Processing

Volumn 2014, Issue 1, 2014, Pages

  Darji, Anand D ^a   Kushwah, Shailendra Singh ^b   Merchant, Shabbir N ^a   Chandorkar, Arun N ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b SARDAR VALLABHBHAI NATIONAL INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Clock gating; Dual scan architecture; DWT; Folding; FPGA; Lifting

Indexed keywords

ADDERS; CLOCKS; DISCRETE WAVELET TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FREQUENCY MULTIPLYING CIRCUITS; LOGIC SYNTHESIS; PIPELINES; SIGNAL RECEIVERS; WAVELET DECOMPOSITION;

2-D DISCRETE WAVELET TRANSFORMS; CLOCK GATING; CLOCK GATING TECHNIQUES; FOLDING; HIGH-PERFORMANCE HARDWARE; LIFTING; LIFTING-BASED DISCRETE WAVELET TRANSFORMS; SCAN ARCHITECTURE;

SIGNAL RECONSTRUCTION;

EID: 84919917254     PISSN: 16875176     EISSN: 16875281     Source Type: Journal    
DOI: 10.1186/1687-5281-2014-47     Document Type: Article

References (23)

1. Daubecies I, Sweldens W: Factoring wavelet transforms into lifting steps.J. Fourier Anal. Appl 1998, 4:247–269. 10.1007/BF02476026
2. Jou J-M, Shiau Y-H, Liu C-C: Efficient VLSI architectures for the bi-orthogonal wavelet transform by filter bank and lifting scheme. In Proc. IEEE International Symposium on Circuits Systems (ISCAS). Sydney, New South Wales; 06–09 May 2001:529–532.
3. Wu B, Lin C: A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec.IEEE Trans. Circuits Syst. Video Technol 2005,15(12):1615–1628.
4. Lai Y-K, Chen L-F, Shih Y-C: A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform.IEEE Trans. Consum. Electron 2009,55(2):400–407.
5. Zhang W, Jiang Z, Gao Z, Liu Y: An efficient VLSI architecture for lifting-based discrete wavelet transform.IEEE Trans. Circuits Syst. II 2012,59(3):158–162.
6. Hsia C-H, Chiang J-S, Guo J-M: Memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform.IEEE Trans. Circuits Syst. Video Technol 2013,25(4):671–683.
7. Darji A, Agrawal S, Oza A, Sinha V, Verma A, Merchant SN, Chandorkar A: Dual-scan parallel flipping architecture for a lifting-based 2-D discrete wavelet transform.IEEE Trans. Circuits Syst. II, Exp. Briefs 2014,61(6):433–437.
8. Andra K, Chakrabarti C, Acharya T: A VLSI architecture for lifting-based forward and inverse wavelet transform.IEEE Trans. Signal Process 2002,50(4):966–977. 10.1109/78.992147
9. Huang C-T, Tseng P-C, Chen L-G: Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. In Proceedings of the IEEE International Symposium on Circuits and Systems. Scottsdale, Arizona; 26–29 May 2002:565–568.
10. Liao H, Mandal MK, Cockburn BF: Efficient architectures for 1-D and 2-D lifting-based wavelet transforms.IEEE Trans. Signal Process 2004,52(5):1315–1326. 10.1109/TSP.2004.826175
11. Chen P-Y: VLSI implementation for one-dimensional multilevel lifting-based wavelet transform.IEEE Trans. Comput 2004,53(4):386–398. 10.1109/TC.2004.1268396
12. Mohanty BK, Meher PK: VLSI architecture for high-speed /low-power implementation of multilevel lifting, DWT. In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems. Singapore; 4–7 Dec 2006:458–461.
13. Xiong C, Tian J, Liu J: Efficient architectures for two-dimensional discrete wavelet transform using lifting scheme.IEEE Trans. Image Process 2007,16(3):607–614.
14. Mohanty BK, Meher PK: Memory efficient modular VLSI architecture for highthroughput and low-latency implementation of multilevel lifting 2-D DWT.IEEE Trans. Signal Process 2011,59(5):2072–2084.
15. Aziz SM, Pham DM: Efficient parallel architecture for multi-level forward discrete wavelet transform processors.J. Comp. Elect. Eng 2012, 38:1325–1335. 10.1016/j.compeleceng.2012.05.009
16. Xiong C-Y, Tian J-W, Liu J: Efficient high-speed/low-power line-based architecture for two-dimensional discrete wavelet transform using lifting scheme.IEEE Trans. Circuits Syst. Video Technol 2006,16(2):309–316.
17. Hsia C-H, Guo J-M, Chiang J-S: Improved low-complexity algorithm for 2-D integer lifting-based discrete wavelet transform using symmetric mask-based scheme.IEEE Trans. Circuits Syst. Video Technol 2009,19(8):1202–1208.
18. Al-Sulaifanie AK, Ahmadi A, Zwolinski M: Very large scale integration architecture for integer wavelet transform.J. IET Comp. Digital Tech 2010,4(6):471–483. 10.1049/iet-cdt.2009.0021
19. Hu Y, Jong CC: A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT.IEEE Trans. Signal Process 2013,61(20):4975–4987.
20. Angelopoulou ME, Masselos K, Cheung PY, Andreopoulos Y: Implementation and comparison of the 5/3 lifting 2-D discrete wavelet transform computation schedules on FPGAs.J. Signal Process. Syst 2008,51(1):3–21. 10.1007/s11265-007-0139-5
21. Mohanty BK, Meher PK: Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT.IEEE Trans. Circuits Syst. Video Technol 2013,23(2):353–363.
22. Barua S, Carletta JE, Kotteri KA, Bell AE: An efficient architecture for lifting-based two-dimensional discrete wavelet transforms.J. Integration, VLSI J 2005,38(3):341–352. 10.1016/j.vlsi.2004.07.010
23. Varshney H, Hasan M, Jain S: Energy efficient novel architectures for the lifting-based discrete wavelet transform.IET Image Process 2007,1(3):305–310. 10.1049/iet-ipr:20060140