Efficient parallel architecture for multi-level forward discrete wavelet transform processors

Computers and Electrical Engineering

Volumn 38, Issue 5, 2012, Pages 1325-1335

  Aziz, Syed Mahfuzul ^a   Pham, Duc Minh ^a  

^a UNIVERSITY OF SOUTH AUSTRALIA   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

DISCRETE WAVELET TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUIT DESIGN; PARALLEL ARCHITECTURES; SIGNAL RECONSTRUCTION;

COMBINATIONAL LOGIC BLOCKS; FORWARD DISCRETE WAVELET TRANSFORMS; GENERIC ARCHITECTURE; HIGH PERFORMANCE ARCHITECTURES; IMAGE PROCESSING APPLICATIONS; PROCESSING ELEMENTS; PROPOSED ARCHITECTURES; SYMMETRIC EXTENSION;

IMAGE PROCESSING;

EID: 84866357907     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2012.05.009     Document Type: Article

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