A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform

IEEE Transactions on Consumer Electronics

Volumn 55, Issue 2, 2009, Pages 400-407

  Lai, Yeong Kang ^a   Chen, Lien Fei ^a   Shih, Yui Chih ^a,b  

^a NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

^b NATIONAL APPLIED RESEARCH LABORATORIES   (Taiwan)

Author keywords

JPEG 2000; Lifting based 2 D DWT architecture; Llifting based discrete wavelet (DWT)

Indexed keywords

COMPARISON RESULT; CRITICAL PATHS; HARDWARE COST; INPUT DATAS; INTERNAL BUFFER; INTERNAL MEMORY; JPEG 2000; LEVEL 2; LIFTING-BASED 2-D DWT ARCHITECTURE; LIFTING-BASED DISCRETE WAVELET TRANSFORMS; LLIFTING-BASED DISCRETE WAVELET (DWT); PIPELINED ARCHITECTURE; SCANNING METHODS; TEMPORAL MEMORY; THROUGHPUT RATE; VLSI ARCHITECTURES;

ARCHITECTURAL DESIGN; DIGITAL TELEVISION; SCANNING; TELEVISION BROADCASTING;

DISCRETE WAVELET TRANSFORMS;

EID: 68949186598     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2009.5174400     Document Type: Article

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