Loose-Ordering Consistency for persistent memory

2014 32nd IEEE International Conference on Computer Design, ICCD 2014

Volumn , Issue , 2014, Pages 216-223

  Lu, Youyou ^a   Shu, Jiwu ^a,b   Sun, Long ^a   Mutlu, Onur ^c  

^a TSINGHUA UNIVERSITY   (China)

^b INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST REDUCTION; DYNAMIC RANDOM ACCESS STORAGE;

CONSISTENCY REQUIREMENTS; DATA PERSISTENCE; EMERGING NON-VOLATILE MEMORY; METADATA INFORMATION; MULTI-VERSIONING; PERFORMANCE DEGRADATION; PERSISTENT MEMORY; STATE OF THE ART;

CACHE MEMORY;

EID: 84919652821     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2014.6974684     Document Type: Conference Paper

References (41)

1. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, "Phase change memory architecture and the quest for scalability, " CACM, 2010.
2. O. Mutlu, "Memory scaling: A systems architecture perspective, " in MEMCON, 2013.
3. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable DRAM alternative, " in ISCA, 2009.
4. M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology, " in ISCA, 2009.
5. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology, " in ISCA, 2009.
6. B. C. Lee, P. Zhou, J. Yang, Y. Zhang et al., "Phase-change technology and the future of main memory, " IEEE Micro, 2010.
7. E. Kultursay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu, "Evaluating STT-RAM as an energy-efficient main memory alternative, " in ISPASS, 2013.
8. G. Dhiman, R. Ayoub, and T. Rosing, "PDRAM: A hybrid PRAM and DRAM main memory system, " in DAC, 2009.
9. H. Yoon, J. Meza, R. Ausavarungnirun, R. A. Harding, and O. Mutlu, "Row buffer locality aware caching policies for hybrid memories, " in ICCD, 2012.
10. J. Condit, E. B. Nightingale, C. Frost, E. Ipek et al., "Better I/O through byte-Addressable, persistent memory, " in SOSP, 2009.
11. X. Wu and A. L. N. Reddy, "SCMFS: A file system for storage class memory, " in SC, 2011.
12. S. R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz et al., "System software for persistent memory, " in EuroSys, 2014.
13. J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp et al., "NV-Heaps: Making persistent objects fast and safe with next-generation, nonvolatile memories, " in ASPLOS, 2011.
14. H. Volos, A. J. Tack, and M. M. Swift, "Mnemosyne: Lightweight persistent memory, " in ASPLOS, 2011.
15. S. Venkataraman, N. Tolia, P. Ranganathan, and R. H. Campbell, "Consistent and durable data structures for non-volatile byte-Addressable memory, " in FAST, 2011.
16. J. Meza, Y. Luo, S. Khan, J. Zhao et al., "A case for efficient hardware/software cooperative management of storage and memory, " in WEED, 2013.
17. C. Mohan, D. Haderle, B. Lindsay, H. Pirahesh, and P. Schwarz, "ARIES: A transaction recovery method supporting fine-granularity locking and partial rollbacks using write-Ahead logging, " TODS, 1992.
18. J. Gray, P. McJones, M. Blasgen, B. Lindsay et al., "The recovery manager of the System R database manager, " ACM Computing Surveys, 1981.
19. V. Prabhakaran, T. L. Rodeheffer, and L. Zhou, "Transactional flash, " in OSDI, 2008.
20. Y. Lu, J. Shu, J. Guo, S. Li, and O. Mutlu, "LightTx: A lightweight transactional design in flash-based SSDs to support flexible transactions, " in ICCD, 2013.
21. J. Coburn, T. Bunker, M. Schwarz, R. Gupta, and S. Swanson, "From ARIES to MARS: Transaction support for next-generation solid-state drives, " in SOSP, 2013.
22. S. C. Tweedie, "Journaling the linux ext2fs filesystem, " in The Fourth Annual Linux Expo, 1998.
23. Y. Lu, J. Shu, and W. Zheng, "Extending the lifetime of flash-based storage through reducing write amplification from file systems, " in FAST, 2013.
24. Y. Lu, J. Shu, and W. Wang, "ReconFS: A reconstructable file system on flash storage, " in FAST, 2014.
25. C. J. Lee, V. Narasiman, E. Ebrahimi, O. Mutlu, and Y. N. Patt, "DRAM-Aware last-level cache writeback: Reducing write-caused interference in memory systems, " HPS Research Group, UT Austin, Tech. Rep., 2010.
26. V. Chidambaram, T. S. Pillai, A. C. Arpaci-Dusseau, and R. H. Arpaci-Dusseau, "Optimistic crash consistency, " in SOSP, 2013.
27. M. K. Qureshi, S. Gurumurthi, and B. Rajendran, "Phase change memory: From devices to systems, " Synthesis Lectures on Computer Architecture, 2011.
28. R. Ramakrishnan and J. Gehrke, Database Management Systems. Osborne/McGraw-Hill, 2000.
29. M. Herlihy and J. E. B. Moss, "Transactional memory: Architectural support for lock-free data structures, " in ISCA, 1993.
30. T. Harris, J. Larus, and R. Rajwar, "Transactional memory, " Synthesis Lectures on Computer Architecture, 2010.
31. Y. Lu, J. Shu, and P. Zhu, "TxCache: Transactional cache using byteaddressable non-volatile memories in SSDs, " in NVMSA, 2014.
32. J. Zhao, S. Li, D. H. Yoon, Y. Xie, and N. P. Jouppi, "Kiln: Closing the performance gap between systems with and without persistence support, " in MICRO, 2013.
33. S. Pelley, P. M. Chen, and T. F. Wenisch, "Memory persistency, " in ISCA, 2014.
34. I. Moraru, D. G. Andersen, M. Kaminsky, N. Binkert et al., "Persistent, protected and cached: Building blocks for main memory data stores, " PDL, CMU, Tech. Rep., 2011.
35. D. Narayanan and O. Hodson, "Whole-system persistence, " in ASPLOS, 2012.
36. Intel, "IntelR 64 and IA-32 architectures software developers manual, " 2014.
37. S. Gopal, T. Vijaykumar, J. Smith, and G. Sohi, "Speculative versioning cache, " in HPCA, 1998.
38. N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt et al., "The Gem5 simulator, " SIGARCH Computer Architecture News, 2011.
39. Graph: Adjacency list, " http://www.boost.org/doc/libs/1 52 0, 2013.
40. LevelDB benchmarks, " http://leveldb.googlecode.com/svn/trunk/doc/ benchmark.html.
41. Sqlite, " http://www.sqlite.org.