An extended BSIM3v3 model card for a vertical 130 nm p-MOSFET

European Solid-State Device Research Conference

Volumn 13-15 Sept. 1999, Issue , 1999, Pages 460-463

  Korbel, A ^a   Mecking, S ^a   Langmann, U ^a   Schulz, T ^b   Aeugle, T ^b   Rosner, W ^b   Risch, L ^b  

^a RUHR UNIVERSITY BOCHUM   (Germany)

^b SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

PARAMETER EXTRACTION;

BSIM3V3 MODELS; CHANNEL LENGTH; GATE RESISTANCE; OPTIMIZATION PROCEDURES; PMOSFET; UNSYMMETRICAL STRUCTURE; VERTICAL MOSFETS;

MOSFET DEVICES;

EID: 84907903473     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. J. E. Brewer, "A new and improved Roadmap", IEEE Cir cuits &Devices, vol. 14, no. 2, 1998, pp. 1318
2. L. Risch et al., "Recent Progress With Vertical Tran sistors", ESSDERC 1997, Proceedings, Stuttgart, 1997, pp. 34-41
3. T. Schulz et al., "130 nm Vertical PMOS Transistors with p+ Poly-Gate", ESSDERC 1998, Proceedings, Bordeaux, 1998, pp. 168-171
4. C. Hu et al., BSIM3v3.2 MOSFET Model User's Manual, University of California, Berkeley, 1998
5. D. R. Pehlke et al., "High. Frequency Application of MOS Compact Models and their Development for Scalable RF Model Libraries", CICC 1998, Proceedings, Santa Clara, 1998, pp. 219-222
6. L. F. Tiemeijer et al., "Geometry Scaling of the Substrate Loss of RF MOSFETs", ESSDERC 1998, Proceedings, Bordeaux, 1998, pp. 480-483
7. X. Jin et al., "An Effective Gate Resistance Model for CMOS RF and Noise Modeling", IEDM 1998, Proceedings, San Francisco, 1998, pp. 961-964
8. D. Klaes et al., "Selectively Grown Vertical Si p-MOS Transistor with Reduced Overlap Capacitances", ESSDERC 1998, Proceedings, Bordeaux, ' 1998, pp. 568-571
9. M. Jurczak et al., "Investigation on the Suitability of Vert ical MOSFET's for High Speed (RF) CMOS Applications", ESSDERC 1998, Proceedings, Bordeaux, 1998, pp. 172-175