Investigation on the suitability of vertical MOSFET's for high speed (RF) CMOS applications

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 172-175

  Jurczak, M ^a,b   Josse, E ^a   Gwoziecki, R ^a   Paoli, M ^a   Skotnicki, T ^a  

^a ORANGE LABS   (France)

^b WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; MOSFET DEVICES;

CAPACITANCE REDUCTION; CURRENT DRIVABILITY; DYNAMIC PERFORMANCE; INTERCONNECT CAPACITANCE; INTRINSIC CAPACITANCE; OVERLAP CAPACITANCE; POLYSILICON GATES; VERTICAL TRANSISTORS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84908154549     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. L. Rish et al., ESSDERC97, p.34.
2. S.C. Sun, IEDM'97, pp.765-768.
3. SIA Road Maps, 1997, p.11.
4. H. Gossner et. al., J. App. Phys, vol .33, p.2423,1994.
5. J.P. Colinge, Kluver Academic Pub\., 1991.
6. F. Balestra, et al, IEEE EIec. Dev. Lett., EDL-8, p.410,1987.