130nm vertical PMOS transistors with P+ poly-gate

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 168-171

  Schulz, T ^a   Rosner, W ^a   Risch, L ^a   Aeugle, T ^a   Langmann, U ^a,b   Korbel, A ^a,b  

^a SIEMENS AG   (Germany)

^b RUHR UNIVERSITY BOCHUM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL CHARACTERISTIC; HIGH INTEGRATION DENSITY; HIGH SATURATION CURRENT; MINIMUM FEATURE SIZES; SELECTIVE EPITAXY; SUBTHRESHOLD SLOPE; TRANSIT FREQUENCY; ULTRA THIN GATE OXIDE;

CMOS INTEGRATED CIRCUITS;

EID: 0004423094     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. H. Takato et al., "High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs" , IEDM Techn. Digest, December 1988, pp. 222-226.
2. L. Risch et al., "Vertical MOS Trans.istors with 70nm Channel Length" , Proceedings of ESSDERC, 1995, pp. 101-103.
3. H. Gossner et al., "Vertical MOS-Technology with Sub-0.1 J.lm Channel Lengths", Elec. Lett. 31,1995, pp. 1394-1396.
4. D. Behammer et al., "Selectiveley Grown Short Channel Vertical Si-p-MOS Transistor For Future Three Dimensional Self Aligned Integration" , Proceedings of ESSDERC, 1996, pp.943-946.
5. H. Iwai, "Recent advantages and future trends of ULSI technology" , Proceedings of ESSDERC, 1996, pp. 45-52.
6. M. C. A. M. Koolen, "An Improved De-Embedding Technique for On-Wafer High-Frequency Characterization" , Proc. IEEE Bip. Cire. And Technol. Meeting, Mineapolis, September 1991.
7. T. Aeugle et al., "Advanced Self Aligned SOl Concepts For Vertical MOS Transistors With Ultrashort Channel Lengths" , Proceedings of ESSDERC, 1997, pp. 628-631