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Volumn 11, Issue 1, 2014, Pages

Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles

Author keywords

Asymmetric workfunction shorted gate; Chip multiprocessor; FinFET; Leakage power; Shorted gate

Indexed keywords

ASYMMETRIC-WORKFUNCTION SHORTED-GATE; CHIP MULTIPROCESSOR; FINFET; LEAKAGE POWER; SHORTED-GATE;

EID: 84907814732     PISSN: 15504832     EISSN: 15504840     Source Type: Journal    
DOI: 10.1145/2629576     Document Type: Article
Times cited : (5)

References (24)
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    • McPAT-PVT: Delay and power modeling framework for FinFET processor architectures under PVT variations
    • To appear
    • A. Tang, Y. Yang, C.-Y. Lee, and N. K. Jha. 2014. McPAT-PVT: Delay and power modeling framework for FinFET processor architectures under PVT variations. IEEE Trans. VLSI Syst. (To appear).
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    • Tang, A.1    Yang, Y.2    Lee, C.-Y.3    Jha, N.K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.