Understanding the design space of DRAM-optimized hardware FFT accelerators

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2014, Pages 248-255

  Akin, Berkin ^a   Franchetti, Franz ^a   Hoe, James C ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; DESIGN; ENERGY EFFICIENCY; ENERGY UTILIZATION; FAST FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; PARETO PRINCIPLE;

ACCELERATOR DESIGN; DATA-INTENSIVE COMPUTING; HARDWARE ACCELERATORS; HARDWARE IMPLEMENTATIONS; MEMORY ACCESS PATTERNS; MEMORY SUBSYSTEMS; PARETO-OPTIMAL DESIGN; TECHNOLOGY SCALING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84906342287     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2014.6868669     Document Type: Conference Paper

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