Computer generation of hardware for linear digital signal processing transforms

ACM Transactions on Design Automation of Electronic Systems

Volumn 17, Issue 2, 2012, Pages

  Milder, Peter ^a   Franchetti, Franz ^a   Hoe, James C ^a   Püschel, Markus ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BEST CHOICE; COMPUTER GENERATION; DATA PATHS; DISCRETE FOURIER TRANSFORM (DFT); EFFICIENCY REQUIREMENTS; FAST FOURIER TRANSFORM ALGORITHM; IP CORE; LINEAR SIGNAL TRANSFORMS; LINEAR TRANSFORM; MATHEMATICAL LANGUAGES; PROBLEM SPECIFICATION; REGISTER TRANSFER LEVEL; RESOURCE BUDGET; TARGET APPLICATION; TRANSFORM ALGORITHM; VERILOG;

ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DESIGN; DIGITAL SIGNAL PROCESSING; DISCRETE FOURIER TRANSFORMS; HARDWARE; MULTIPROCESSING SYSTEMS;

MATHEMATICAL TRANSFORMATIONS;

EID: 84860271858     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/2159542.2159547     Document Type: Article

References (32)

1. 4DSP, LLC. 2007. 4DSP floating point fast Fourier transform V2.6. 4DSP, LLC.
2. ASTOLA, J. AND AKOPIAN, D. 1999. Architecture-oriented regular algorithms for discrete sine and cosine transforms. IEEE Trans. Signal Process. 47, 4, 1109-1124.
3. BLUESTEIN, L. I. 1970. A linear filtering approach to computation of discrete Fourier transform. IEEE Trans. Audio Electroacoust. 18, 4, 451-455.
4. COHEN, D. 1976. Simplified control of FFT hardware. IEEE Trans. Acoust. Speech, Signal Process. 24, 6, 577-579. (Pubitemid 8130655)
5. COOLEY, J. W. AND TUKEY, J. W. 1965. An algorithm for the machine calculation of complex Fourier series. Math. Computat. 19, 90, 297-301.
6. k FFTs: Matricial representation and SDC/SDF pipeline implementation. IEEE Trans. Signal Process. 57, 7, 2824-2839.
7. DAVE, N., PELLAUER, M., GERDING, S., AND ARVIND. 2006. 802.11a transmitter: A case study in microarchitectural exploration. In Proceedings of the ACM/IEEE International Conference on Formal Methods and Models for Codesign. 59-68. (Pubitemid 351410292)
8. DERSHOWITZ, N. AND PLAISTED, D. A. 2001. Rewriting. In Handbook of Automated Reasoning, Vol. 1, A. Robinson and A. Voronkov Eds., Elsevier, 535-610.
9. FRANCHETTI, F., VORONENKO, Y., AND PÜSCHEL, M. 2006a. FFT program generation for shared memory: SMP and multicore. In Proceedings of the ACM/IEEE Conference on Supercomputing.
10. FRANCHETTI, F., VORONENKO, Y., AND PÜSCHEL, M. 2006b. A rewriting system for the vectorization of signal transforms. In Proceedings of High Performance Computing for Computational Science (VECPAR). Lecture Notes in Computer Science, vol. 4395, Springer, 363-377.
11. GORMAN, S. F. AND WILLS, J. M. 1995. Partial column FFT pipelines. IEEE Trans. Circuits Syst. II: Analog Digital Signal Process. 42, 6, 414-423.
12. HE, S. AND TORKELSON, M. 1996. A new approach to pipeline FFT processor. In Proceedings of the International Parallel Processing Symposium. 766-770.
13. JÄRVINEN, T. S., SALMELA, P., SOROKIN, H., AND TAKALA, J. H. 2004. Stride permutation networks for array processors. In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors. 51-71.
14. JOHNSON, J. R., JOHNSON, R. W., RODRIGUEZ, D., AND TOLIMIERI, R. 1990. A methodology for designing, modifying, and implementing Fourier transform algorithms on various architectures. Circuits, Syst. Signal Process. 9, 449-500.
15. KEE, H., PETERSEN, N., KORNERUP, J., AND BHATTACHARYYA, S. S. 2008. Systematic generation of FPGA-based FFT implementations. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing. 1413-1416.
16. KUMHOM, P., JOHNSON, J., AND NAGVAJARA, P. 2000. Design, optimization, and implementation of a universal FFT processor. In Proceedings of the 13th IEEE ASIC/SOC Conference. 182-186.
17. MILDER, P. A. 2010. A mathematical approach for compiling and optimizing hardware implementations of DSP transforms. Ph. D. dissertation, Electrical and Computer Engineering, Carnegie Mellon University.
18. MILDER, P. A., AHMAD, M., HOE, J. C., AND PÜSCHEL, M. 2006. Fast and accurate resource estimation of automatically generated custom DFT IP cores. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA). 211-220. (Pubitemid 44032254)
19. MILDER, P. A., FRANCHETTI, F., HOE, J. C., AND PÜSCHEL, M. 2008. Formal datapath representation and manipulation for implementing DSP transforms. In Proceedings of the 45th Annual ACM/IEEE Conference on Design Automation (DAC). 385-390.
20. MILDER, P. A., HOE, J. C., AND PÜSCHEL, M. 2009. Automatic generation of streaming datapaths for arbitrary fixed permutations. In Proceedings of the Conference and Exhibition on Design, Automation and Test in Europe. 1118-1123.
21. MURALIMANOHAR, N., BALASUBRAMONIAN, R., AND JOUPPI, N. P. 2009. CACTI 6.0: A tool to model large caches. Tech. rep. HPL-2009-85, Hewlett-Packard Laboratories.
22. NIKARA, J., TAKALA, J. H., AND ASTOLA, J. 2006. Discrete cosine and sine transforms-regular algorithms and pipeline architectures. Signal Process., 230-249. (Pubitemid 41709496)
23. PEASE, M. C. 1968. An adaptation of the fast Fourier transform for parallel processing. J. ACM 15, 2, 252-264.
24. PÜSCHEL, M., MOURA, J. M. F., JOHNSON, J., PADUA, D., VELOSO, M., SINGER, B. W., XIONG, J., FRANCHETTI, F., GAČIĆ, A., VORONENKO, Y., CHEN, K., JOHNSON, R. W., AND RIZZOLO, N. 2005. SPIRAL: Code generation for DSP transforms. Proc. IEEE 93, 2, 232-275.
25. PÜSCHEL, M., MILDER, P. A., AND HOE, J. C. 2009. Permuting streaming data using RAMs. J. ACM 56, 2.
26. SUKHSAWAS, S. AND BENKRID, K. 2004. A high-level implementation of a high performance pipeline FFT on Virtex-E FPGAs. In Proceedings of the IEEE Symposium on VLSI. 229-232.
27. TAKALA, J. H., AKOPIAN, D. A., ASTOLA, J., AND SAARINEN, J. P. P. 2000. Constant geometry algorithm for discrete cosine transform. IEEE Trans. Signal Process. 48, 6, 1840-1843.
28. VAN LOAN, C. 1992. Computational Frameworks for the Fast Fourier Transform. SIAM.
29. VORONENKO, Y. AND PÜSCHEL, M. 2009. Algebraic signal processing theory: Cooley-Tukey type algorithms for real DFTs. IEEE Trans. Signal Process. 57, 1, 205-222.
30. XILINX, INC. 2010. Xilinx LogiCore IP fast Fourier transform v7.1. Xilinx, Inc.
31. XIONG, J., JOHNSON, J., JOHNSON, R., AND PADUA, D. 2001. SPL: A language and compiler for DSP algorithms. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI). 298-308.
32. ZAPATA, E. L. AND ARGÜELLO, F. 1992. A VLSI constant geometry architecture for the fast Hartley and Fourier transforms. IEEE Trans. Parall. Distrib. Syst. 3, 1, 58-70.