A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2014, Pages

  Elshazly, Amr ^a   Balankutty, Ajay ^a   Huang, Yan Yu ^a   Yu, Kai ^a   O'Mahony, Frank ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; ENERGY EFFICIENCY;

DIGITAL DELAY-LOCKED LOOPS; DIGITAL LOOP FILTERS; ENERGY EFFICIENT; LONG-TERM JITTER; MULTI-STANDARD; OUTPUT FREQUENCY; QUADRATURE CLOCKS; STATE OF THE ART;

VLSI CIRCUITS;

EID: 84905670644     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2014.6858375     Document Type: Conference Paper

References (5)

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3. K. Bhardwaj, et al., "A 3.1mW phase-tunable quadrature generation method for CEI 28G short-reach CDR in 28nm CMOS," ISSCC, 2013.
4. A. Arakali, et al., "Low-power supply-regulation techniques for ring oscillators in phase-locked loops using a split-tuned architecture," JSSC, Aug. 2009.
5. T. Toifl, et al., "A 1.25-5 GHz clock generator with highbandwidth supply-rejection using a regulated-replica regulator in 45-nm CMOS," JSSC, Nov. 2009.