A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 412-413

  Bhardwaj, Kanupriya ^a   Narayan, Sriram ^b   Shumarayev, Sergey ^c   Lee, Thomas ^a  

^a STANFORD UNIVERSITY   (United States)

^b Inphi   (United States)

^c Altera   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

28NM CMOS; CLOCK SYSTEMS; DATA RATES; HALF-RATE; HALF-RATE CLOCK; POWER OVERHEAD; QUADRATURE GENERATION; RING OSCILLATOR;

EMBEDDED SYSTEMS; VARIABLE FREQUENCY OSCILLATORS;

CLOCKS;

EID: 84876522886     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487793     Document Type: Conference Paper

References (6)

1. J. Bulzacchelli, et al., "A 28Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32nm SOI CMOS Technology," ISSCC Dig. Tech. Papers, pp. 324-326, Feb. 2012
2. CEI-28G-SR Working Clause Proposal, OIF-CEI-03.0, Sept. 2011. Available: Http://www/oiforum.com/public/documents/OIF-CEI-03.0.pdf
3. F. O'Mahony, et al., "A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS," ISSCC Dig. Tech. Papers, pp. 452-453, Feb. 2008
4. S. Ranganathan and Y. Tsividis, "Discrete-Time Parametric Amplification Based on a Three-Terminal MOS Varactor: Analysis and Experimental Results," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2087-2093, Dec. 2003
5. C.-F. Liao and S.-I. Liu, "A 40 Gb/s CMOS Serial-link Receiver with Adaptive Equalization and Clock/Data Recovery," IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2492-2502, Nov. 2008
6. A.Y. Valero-Lopez, S.T. Moon, and E. Sanchez-Sinencio, "Self-Calibrated Quadrature Generator for WLAN Multistandard Frequency Synthesizer," IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1031-1041, May 2006