A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 326-327

  Harwood, Mike ^a   Nielsen, Steffen ^b   Szczepanek, Andre ^a   Allred, Richard ^b   Batty, Sean ^a   Case, Mike ^b   Forey, Simon ^a   Gopalakrishnan, Karthik ^b   Kan, Larry ^b   Killips, Bob ^a   Mishra, Parmanand ^b   Pande, Rohit ^b   Rategh, Hamid ^b   Ren, Alan ^b   Sanders, Jeff ^b   Schoy, Albrecht ^b   Ward, Richard ^b   Wetterhorn, Martin ^b   Yeung, Norman ^b  

^a Inphi   (United Kingdom)

^b Inphi   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG EQUALIZATION; JITTER PERFORMANCE; LOW-POWER TRANSCEIVER; OPTICAL NETWORKING; OPTICAL SUBASSEMBLY; OPTICAL TRANSPORT; RETIMING; SIGE TECHNOLOGY;

TIMING JITTER;

EID: 84860700124     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177032     Document Type: Conference Paper

References (7)

1. K Wu et al, "A 2 x 25Gb/s receiver with 2:5 DMUX for 100Gb/s Ethernet."
2. OIF2010.404.04: CEI-28G-VSR draft IA.
3. IEEE 802.3ba 22 June 2010 Part 3: CSMA/CD Access Method and Physical Layer Specifications.
4. A. K. Joy et al., "Analog DFE Based 16Gb/s SerDes in 40nm CMOS that operates across 34dB Loss channels at Nyquist with a baud rate CDR and 1.2V voltage mode driver," ISSCC Dig Tech Papers, pp. 350-351, Feb. 2011.
5. M Harwood, N Warke et al., "A 12.5 Gb/s SerDes in 65nm CMOS using a baud rate CDR with Digital Receiver Equalization and Clock Recovery," ISSCC Dig Tech Papers, pp. 436-7, Feb. 2007.
6. C Mentofi et al., "A 16Gb/s Source Series Terminated Transmitter in 65nm CMOS SOI," ISSCC Dig Tech Papers, pp. 446-7, Feb 2007.
7. D Kam et al., "Is 25Gb/s On-board Signalling Viable?," IEEE Transactions on Advanced Packaging, vol. 32, no. 2, May 2009.