Multi-stage coordinated prefetching for present-day processors

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2014, Pages 73-82

  Mehta, Sanyam ^a   Fang, Zhenman ^b   Zhai, Antonia ^a   Yew, Pen Chung ^a  

^a University of Minnesota   (United States)

^b FUDAN UNIVERSITY   (China)

Author keywords

coordinated prefetching; sandybridge; xeonphi

Indexed keywords

HARDWARE; MICROPROCESSOR CHIPS; MULTICORE PROGRAMMING; PROGRAM COMPILERS;

ARCHITECTURAL FEATURES; HARDWARE AND SOFTWARE; HIDING MEMORY LATENCY; PREFETCHING; PREFETCHING TECHNIQUES; SANDYBRIDGE; SOFTWARE PREFETCHING; XEONPHI;

PIPELINE PROCESSING SYSTEMS;

EID: 84903761716     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2597652.2597660     Document Type: Conference Paper

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