Leakage control in 0.4-nm EOT Ru/SrTiOx/Ru metal-insulator-metal capacitors: Process Implications

IEEE Electron Device Letters

Volumn 35, Issue 7, 2014, Pages 753-755

  Swerts, Johan ^a   Popovici, Mihaela ^a   Kaczer, Ben ^a   Aoulaiche, Marc ^a   Redolfi, Augusto ^a   Clima, Sergiu ^a   Caillat, Christian ^b   Wang, Wan Chih ^c   Afanasev, Valeri V ^c   Jourdan, Nicolas ^a   Olk, Christina ^a   Hody, Hubert ^a   Van Elshocht, Sven ^a   Jurczak, Malgorzata ^a  

^a IMEC   (Belgium)

^b MICRON TECHNOLOGY INC   (United States)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Capacitors; dielectric devices; DRAM; leakage currents; Ru

Indexed keywords

ATOMIC LAYER DEPOSITION; CAPACITORS; DEPOSITION; DIELECTRIC DEVICES; DYNAMIC RANDOM ACCESS STORAGE; ELECTRODES; LEAKAGE CURRENTS; METAL INSULATOR BOUNDARIES; MIM DEVICES; RUTHENIUM;

CRUCIAL PARAMETERS; DEPOSITION TECHNIQUE; LEAKAGE CONTROL; METAL INSULATOR METAL CAPACITOR (MIM); POST-DEPOSITION ANNEAL; SRTIO; TOP-ELECTRODE MATERIALS;

ELECTROLYTIC CAPACITORS;

EID: 84903595149     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2014.2322632     Document Type: Article

References (14)

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