Self-aligned through silicon vias in ultra-thin chips for 3D-integration

2012 4th Electronic System-Integration Technology Conference, ESTC 2012

Volumn , Issue , 2012, Pages

  Ferwana, Saleh ^a   Harendt, Christine ^a   Letzkus, Florian ^a   Burghartz, Joachim N ^a  

^a Institut fur Mikroelektronik Stuttgart   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANCHORS; ELECTRONICS ENGINEERING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATION; SILICON; SILICON OXIDES;

ETCHING PROCESS; HIGH SELECTIVITY; OXIDIZED SILICON; SELF-ALIGNED; SILICON VIA; THERMAL OXIDATION; THROUGH SILICON VIAS; ULTRA-THIN CHIPS;

TECHNOLOGY;

EID: 84902504577     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2012.6542114     Document Type: Conference Paper

References (10)

1. R. S. Patti, "Three dimensional integrated circuits and the future of system-on-chip designs", Proc. IEEE, Vol. 94, no. 6 (2006), pp. 1214.1224.
2. K. Wook et al., "Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip," Jpn. J. App. Phys. Vol. 39 (2000), pp. 2473-2477.
3. E. Beyne et al., "Through-Silicon Via and Die Stacking Technologies for Micro Systems Integration," in Tech. Dig. IEDM, 2008, pp. 1-4.
4. S. Takyu et al., "Novel Wafer Dicing and Chip Thinning Technologies Realizing High Chip Strength", El. Compo. and Tech. Conf., 2006, pp. 1623-1627.
5. V.P. Ganesh and C. lee, "Overview and emerging challenges in wafer thinning process for handheld applications", Proc. Int. Electr. Manuf. Tech., 2006, pp. 20-26
6. M. Zimmermann et al., "A Seamless Ultra-Thin Chip Fabrication and Assembly Technology", Techn. Dig. IEDM 2006, pp. 1010-1012, 2006.
7. E. A. Angelopoulos et al., "Ultra-Thin Chip Technology for System-in-Foil Applications," Techn. Dig. IEDM 2010, pp. 2.5.1-2.5.4, 2010.
8. F. Laermer et al., "Bosch deep silicon etching: improving uniformity and etch rate for for advanced MEMS applications", Twelfth IEEE International Conference on Micro Electro Mechanical Systems 1999, MEMS 99.
9. S. Ferwana et al., "Through Silicon Via technology in Chipfilm™ substrate for 3D integration", Poster presentation, in ICT.OPEN 2011, November 14-15, 2011, Veldhoven, The Netherland, pp. 63-66, (2011).
10. A. Shareef et al., "Subatmospherical chemical vapour deposition ozone/TEOS process for SiO2 trench filling", J. Vac. Sci. Technol. B 13(4), Jul/Aug 1995, pp. 1888-1892.