Ultra-thin chip technology for system-in-foil applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Angelopoulos, Evangelos A ^a   Zimmermann, Martin ^a   Appel, Wolfgang ^a   Endler, Stefan ^a   Ferwana, Saleh ^a   Harendt, Christine ^a   Hoang, Tu ^a   Pruemm, Andreas ^a   Burghartz, Joachim N ^a  

^a Institut fur Mikroelektronik Stuttgart   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLIED STRESS; CMOS MANUFACTURING; MECHANICAL FLEXIBILITY; PROCESS WINDOW; SILICON CHIP; SILICON MEMBRANES; SILICON SUBSTRATES; ULTRA-THIN CHIPS;

ANCHORS; ELECTRON DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SURFACE TOPOGRAPHY;

SILICON WAFERS;

EID: 79951823772     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703284     Document Type: Conference Paper

References (6)

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2. J. N. Burghartz et al., "Ultra-Thin Chips and Relate Aplications, A New Paradigm in Silicon Technology", in Proc. of ESSDERC-ESSDIRC 2009, pp.29-36, 2009.
3. th International Forum be-flexible, Munich, 2008.
4. R. Dekker et al., "Substrate Transfer: an Enabling Technology for System-in-Package Solutions", Bipolar/BiCMOS Circuits and Technology Meeting 2006, 2006.
5. Eun-Kyung Kim, "Assessment of ultra-thin Si wafer thickness in 3D wafer stacking", Microelectronics Reliability, vol.50, pp.195-198, 2010.
6. J. N. Burghartz et al., "A New Fabrication and Assempbly Process for Ultrathin Chips", IEEE Trans. On El. Devices, vol.56, pp.321-327, 2009.