메뉴 건너뛰기




Volumn 4, Issue 2, 2014, Pages 80-85

Energy-prediction scheduler for reconfigurable systems in energy-harvesting environment

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; RECONFIGURABLE HARDWARE; WIRELESS SENSOR NETWORKS;

EID: 84901912553     PISSN: 20436386     EISSN: 20436394     Source Type: Journal    
DOI: 10.1049/iet-wss.2012.0129     Document Type: Article
Times cited : (6)

References (25)
  • 2
    • 17044365390 scopus 로고    scopus 로고
    • Energy scavenging for mobile and wireless electronics
    • Paradiso, J.A., Starner, T.: 'Energy scavenging for mobile and wireless electronics', IEEE Pervasive Comput., 2005, 4, (1), pp. 18-27
    • (2005) IEEE Pervasive Comput. , vol.4 , Issue.1 , pp. 18-27
    • Paradiso, J.A.1    Starner, T.2
  • 4
    • 84896915296 scopus 로고    scopus 로고
    • Solar energy harvesting for autonomous field devices
    • DOI: 10.1049/iet-wss.2013.0011, Available online: 05 September 2013
    • Decker, A.: 'Solar energy harvesting for autonomous field devices', IET Wirel. Sensor Syst., 2013, pp. 8, DOI: 10.1049/iet-wss.2013.0011, Available online: 05 September 2013
    • IET Wirel. Sensor Syst. , vol.2013 , pp. 8
    • Decker, A.1
  • 8
    • 84879348771 scopus 로고    scopus 로고
    • Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems
    • Yang, X., Zhang, Y., Liu, D., et al.: 'Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems', IET Wirel. Sensor Syst., 2013, 3, (2), pp. 119-125
    • (2013) IET Wirel. Sensor Syst. , vol.3 , Issue.2 , pp. 119-125
    • Yang, X.1    Zhang, Y.2    Liu, D.3
  • 9
    • 79952847670 scopus 로고    scopus 로고
    • Adaptable security in wireless sensor networks by using reconfigurable ecc hardware coprocessors
    • doi: 10.1155/2010/740823
    • Portilla, J., Otero, A., de la Torre, E., et al.: 'Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors', Int. J. Distributed Sensor Netw., 2010, 2010, doi: 10.1155/2010/740823
    • (2010) Int. J. Distributed Sensor Netw. , pp. 2010
    • Portilla, J.1    Otero, A.2    De La Torre, E.3
  • 10
    • 39649110473 scopus 로고    scopus 로고
    • Dynamic and partial fpga exploitation
    • Becker, J., Hubner, M., Hettich, G., et al.: 'Dynamic and partial FPGA exploitation', Proc. IEEE, 2007, 95, (2), pp. 438-452
    • (2007) Proc. IEEE , vol.95 , Issue.2 , pp. 438-452
    • Becker, J.1    Hubner, M.2    Hettich, G.3
  • 11
    • 34548072006 scopus 로고    scopus 로고
    • Run-time integration of reconfigurable video processing systems
    • Sedcole, P., Peter, Y.K., George, C., et al.: 'Run-time integration of reconfigurable video processing systems', IEEE Trans. VLSI Syst., 2007, 15, (9), pp. 1003-1016
    • (2007) IEEE Trans. VLSI Syst. , vol.15 , Issue.9 , pp. 1003-1016
    • Sedcole, P.1    Peter, Y.K.2    George, C.3
  • 14
  • 15
    • 79960997045 scopus 로고    scopus 로고
    • Embedded runtime reconfigurable nodes for wireless sensor networks applications
    • Krasteva, Y.E., Portilla, J., de la Torre, E., et al.: 'Embedded runtime reconfigurable nodes for wireless sensor networks applications', IEEE Sens. J., 2011, 11, (9), pp. 1800-1810
    • (2011) IEEE Sens. J. , vol.11 , Issue.9 , pp. 1800-1810
    • Krasteva, Y.E.1    Portilla, J.2    De La Torre, E.3
  • 16
    • 84859028491 scopus 로고    scopus 로고
    • Using sram based fpgas for power-aware high performance wireless sensor networks
    • Valverde, J., Otero, A., Lopez, M., et al.: 'Using SRAM based FPGAs for power-aware high performance wireless sensor networks', Sensors, 2012, 12, (3), pp. 2667-2692
    • (2012) Sensors , vol.12 , Issue.3 , pp. 2667-2692
    • Valverde, J.1    Otero, A.2    Lopez, M.3
  • 17
    • 84866916574 scopus 로고    scopus 로고
    • Hardware reconfigurable wireless sensor network node with power and area efficiency
    • Li, Y., Jia, Z., Liu, F.: 'Hardware reconfigurable wireless sensor network node with power and area efficiency', IET Wirel. Sens. Syst., 2012, 2, (3), pp. 247-252
    • (2012) IET Wirel. Sens. Syst. , vol.2 , Issue.3 , pp. 247-252
    • Li, Y.1    Jia, Z.2    Liu, F.3
  • 20
    • 84876223442 scopus 로고    scopus 로고
    • Dynamically reconfigurable hardware with a novel scheduling strategy in energy-harvesting sensor networks
    • Li, Y., Jia, Z., Xie, S., Liu, F.: 'Dynamically reconfigurable hardware with a novel scheduling strategy in energy-harvesting sensor networks', IEEE Sens. J., 2013, 13, (5), pp. 2032-2038
    • (2013) IEEE Sens. J. , vol.13 , Issue.5 , pp. 2032-2038
    • Li, Y.1    Jia, Z.2    Xie, S.3    Liu, F.4
  • 22
    • 33646431967 scopus 로고    scopus 로고
    • Modular dynamic reconfiguration in virtex fpgas
    • Sedcole, P., Blodget, B., Becker, T., et al.: 'Modular dynamic reconfiguration in Virtex FPGAs', IEE Proc.-Comput. Digit. Tech., 2006, 153, (3), pp. 157-164
    • (2006) IEE Proc.-Comput. Digit. Tech. , vol.153 , Issue.3 , pp. 157-164
    • Sedcole, P.1    Blodget, B.2    Becker, T.3
  • 23
    • 84947928278 scopus 로고    scopus 로고
    • Automated method to generate bitstream intellectual property cores for virtex fpgas
    • Horta, E.L., Lockwood, J.W.: 'Automated method to generate bitstream intellectual property cores for Virtex FPGAs'. Proc. FPL04, Leuven, Belgium, 2004, pp. 975-979
    • (2004) Proc. FPL04, Leuven, Belgium , pp. 975-979
    • Horta, E.L.1    Lockwood, J.W.2
  • 24
    • 33749061304 scopus 로고    scopus 로고
    • Sense bench: Toward an accurate evaluation of sensor network processors
    • Nazhandali, L., Minuth, M., Austin, T.: 'Sense bench: toward an accurate evaluation of sensor network processors'. Proc. of IISWC, Austin, TX, 2005, pp. 197-203
    • (2005) Proc. Of IISWC, Austin, TX , pp. 197-203
    • Nazhandali, L.1    Minuth, M.2    Austin, T.3
  • 25
    • 47649096627 scopus 로고    scopus 로고
    • Exploring the processor and isa design for wireless sensor network applications
    • Mysore, S., Agrawal, B., Chong, F., et al.: 'Exploring the processor and ISA design for wireless sensor network applications'. Proc. of VLSI'08, Hyderabad, India, 2008, pp. 59-64
    • (2008) Proc. Of VLSI'08, Hyderabad, India , pp. 59-64
    • Mysore, S.1    Agrawal, B.2    Chong, F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.