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Volumn 2, Issue 3, 2012, Pages 247-252

Hardware reconfigurable wireless sensor network node with power and area efficiency

Author keywords

[No Author keywords available]

Indexed keywords

AREA COST; AREA EFFICIENCY; AREA SAVINGS; CONFIGURATION FILES; LOW-POWER CONSUMPTION; NODE ARCHITECTURES; PERFORMANCE IMPROVEMENTS; PROCESS INFORMATION; PROCESSING SPEED; SOFTWARE APPROACH; TEST CASE; WIRELESS SENSOR; WIRELESS SENSOR NETWORK (WSNS); WORK-FLOWS;

EID: 84866916574     PISSN: 20436386     EISSN: 20436394     Source Type: Journal    
DOI: 10.1049/iet-wss.2011.0162     Document Type: Article
Times cited : (8)

References (24)
  • 2
    • 51849135018 scopus 로고    scopus 로고
    • An enhanced sensor scheduling protocol for wireless sensor networks
    • 28th, Beijing, China, June, 17-20
    • Fu, C.W., Lim, B., and Beng, H.: ' An enhanced sensor scheduling protocol for wireless sensor networks ', 28th, Int. Conf. on Distributed Comp Sys Workshops, 2008, ICDCS'08, Beijing, China, June, 17-20, 2008, p. 303-308
    • (2008) Int. Conf. on Distributed Comp Sys Workshops, 2008, ICDCS'08 , pp. 303-308
    • Fu, C.W.1    Lim, B.2    Beng, H.3
  • 5
    • 34547979431 scopus 로고    scopus 로고
    • Features, design tools, and application domain of FPGAs
    • 10.1109/TIE.2007.898279 0278-0046
    • Rodrigez-Andina, J.J., Moure, M.J., and Valdes, M.D.: ' Features, design tools, and application domain of FPGAs ', IEEE Trans. Ind. Electron., 2007, 54, (4), p. 1810-1823 10.1109/TIE.2007.898279 0278-0046
    • (2007) IEEE Trans. Ind. Electron. , vol.54 , Issue.4 , pp. 1810-1823
    • Rodrigez-Andina, J.J.1    Moure, M.J.2    Valdes, M.D.3
  • 6
    • 0031343311 scopus 로고    scopus 로고
    • Seeking solutions in configurable computing
    • et al. ' ', , 10.1109/2.642810
    • Mangione-Smith, W.H., Hutchings, B., and Andrews, D.: et al. ' Seeking solutions in configurable computing ', IEEE Comput., 1997, 30, (12), p. 38-43 10.1109/2.642810
    • (1997) IEEE Comput. , vol.30 , Issue.12 , pp. 38-43
    • Mangione-Smith, W.H.1    Hutchings, B.2    Andrews, D.3
  • 11
    • 39649110473 scopus 로고    scopus 로고
    • Amic and partial FPGA exploitation
    • et al. ' ', , 10.1109/JPROC.2006.888404 0018-9219
    • Becker, J., Hubner, M., and Hettich, G.: et al. ' Amic and partial FPGA exploitation ', Proc. IEEE, 2007, 92, (2), p. 438-452 10.1109/JPROC.2006.888404 0018-9219
    • (2007) Proc. IEEE , vol.92 , Issue.2 , pp. 438-452
    • Becker, J.1    Hubner, M.2    Hettich, G.3
  • 12
    • 34548072006 scopus 로고    scopus 로고
    • Run-time integration of reconfigurable video processing systems
    • 10.1109/TVLSI.2007.902203 1063-8210
    • Sedcole, P., Peter, Y.K., George, C., Constantinides, A., and Luk, W.: ' Run-time integration of reconfigurable video processing systems ', IEEE Trans. VLSI Syst., 2007, 15, (9), p. 1003-1016 10.1109/TVLSI.2007.902203 1063-8210
    • (2007) IEEE Trans. VLSI Syst. , vol.15 , Issue.9 , pp. 1003-1016
    • Sedcole, P.1    Peter, Y.K.2    George, C.3    Constantinides, A.4    Luk, W.5
  • 13
    • 54949088306 scopus 로고    scopus 로고
    • Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor
    • Heidelberg, Germany, September, 8-10
    • Zaidi, S.I.H., Nabina, A., Canagarajah, C.N., and Nunez-Yanez, J.: ' Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor ', Proc. FPL, Heidelberg, Germany, September, 8-10, 2008, p. 547-550
    • (2008) Proc. FPL , pp. 547-550
    • Zaidi, S.I.H.1    Nabina, A.2    Canagarajah, C.N.3    Nunez-Yanez, J.4
  • 14
    • 79960997045 scopus 로고    scopus 로고
    • Embedded runtime reconfigurable nodes for wireless sensor networks applications Krasteva
    • 10.1109/JSEN.2011.2104948 1530-437X
    • Krasteva, Y.E., Portilla, J., de la Torre, E., and Riesgo, T.: ' Embedded runtime reconfigurable nodes for wireless sensor networks applications Krasteva ', IEEE Sens. J., 2011, 11, (9), p. 1800-1810 10.1109/JSEN.2011.2104948 1530-437X
    • (2011) IEEE Sens. J. , vol.11 , Issue.9 , pp. 1800-1810
    • Krasteva, Y.E.1    Portilla, J.2    De La Torre, E.3    Riesgo, T.4
  • 15
    • 84866887790 scopus 로고    scopus 로고
    • accessed April 2007
    • http://www.robotics.eecs.berkeley.edu/~pister/SmartDust/, accessed April 2007
  • 16
    • 84866948450 scopus 로고    scopus 로고
    • accessed June 2009
    • http://www.jlhlabs.com/, accessed June 2009
  • 17
    • 84866887789 scopus 로고    scopus 로고
    • accessed July 2009
    • http://www.nesl.ee.ucla.edu/projects/ahlos/mk2, accessed July 2009
  • 19
    • 33645989083 scopus 로고    scopus 로고
    • The development of a novel miniaturized modular platform for wireless sensor networks
    • et al. ' ', Los Angeles, USA, April
    • O'Flynn, B., Bellis, S., and Delaney, K.: et al. ' The development of a novel miniaturized modular platform for wireless sensor networks ', Proc. Fourth Int. Symp. Inform. Process. Sensor Networks, IPSN'05, Los Angeles, USA, April, 2005, p. 370-375
    • (2005) Proc. Fourth Int. Symp. Inform. Process. Sensor Networks, IPSN'05 , pp. 370-375
    • O'Flynn, B.1    Bellis, S.2    Delaney, K.3
  • 20
    • 84866948449 scopus 로고    scopus 로고
    • accessed May 2009
    • www.gaisler.com/, accessed May 2009
  • 22
    • 84947928278 scopus 로고    scopus 로고
    • Automated method to generate bitstream intellectual property cores for Virtex FPGAs
    • Leuven, Belgium, August
    • Horta, E.L., and Lockwood, J.W.: ' Automated method to generate bitstream intellectual property cores for Virtex FPGAs ', Proc. 14th Field-Programmable Logic and Applications, FPL04, Leuven, Belgium, August, 2004, p. 975-979
    • (2004) Proc. 14th Field-Programmable Logic and Applications, FPL04 , pp. 975-979
    • Horta, E.L.1    Lockwood, J.W.2
  • 23
    • 33749061304 scopus 로고    scopus 로고
    • Sense bench: Toward an accurate evaluation of sensor network processors
    • Austin, TX, October
    • Nazhandali, L., Minuth, M., and Austin, T.: ' Sense bench: toward an accurate evaluation of sensor network processors ', Proc. IISWC, Austin, TX, October, 2005, p. 197-203
    • (2005) Proc. IISWC , pp. 197-203
    • Nazhandali, L.1    Minuth, M.2    Austin, T.3
  • 24
    • 47649096627 scopus 로고    scopus 로고
    • Exploring the processor and ISA design for wireless sensor network applications
    • Hyderabad, India, January
    • Mysore, S., Agrawal, B., Chong, F., and Sherwood, T.: ' Exploring the processor and ISA design for wireless sensor network applications ', Proc. VLSI'08, Hyderabad, India, January, 2008, p. 59-64
    • (2008) Proc. VLSI'08 , pp. 59-64
    • Mysore, S.1    Agrawal, B.2    Chong, F.3    Sherwood, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.